We present a low-power reconfigurable DCT architecture, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our DCT implementation. A low power reconfigurable DCT architecture is exploited by making a trade off between image quality and power consumption. The proposed DCT architecture was implemented using 0.35μ technology. The experimental results show that reconfigurable DCT using CSHM can improve power consumption by 40% without noticeable image quality degradation.
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|Publication status||Published - 2002|
|Event||2002 IEEE International Conference on Acoustic, Speech, and Signal Processing - Orlando, FL, United States|
Duration: 2002 May 13 → 2002 May 17
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering