Low-power Skewed Static Logic (S 2L) with topology-dependent dual Vt

Chulwoo Kim, Jaesik Lee, Kwang Hyun Baek, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we describe Skewed Static Logic (S 2L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S 2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Noise-tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S 2L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S 2L with dual Vt reduces delay by 43% and energy×delay by 31% for 1 V power supply over conventional CMOS circuit.

Original languageEnglish
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublisherIEEE
Pages310-314
Number of pages5
Publication statusPublished - 2000
Externally publishedYes
EventProceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Duration: 2000 Sep 132000 Sep 16

Other

OtherProceedings of the 13th Annual IEEE International ASIC/SOC Conference
CityArlington, VA, USA
Period00/9/1300/9/16

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kim, C., Lee, J., Baek, K. H., & Kang, S. M. (2000). Low-power Skewed Static Logic (S 2L) with topology-dependent dual Vt In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 310-314). IEEE.