In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Noise-tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S2L with dual Vt reduces delay by 43% and energy×delay by 31% for 1 V power supply over conventional CMOS circuit.
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|Publication status||Published - 2000|
|Event||Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA|
Duration: 2000 Sep 13 → 2000 Sep 16
ASJC Scopus subject areas
- Electrical and Electronic Engineering