A 1 GHz DLL-based clock generator in 0.35 μm CMOS occupies 0.08 mm2. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems, Measured peak-to-peak jitter is ±7.28 ps.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2002|
|Event||2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States|
Duration: 2002 Feb 3 → 2002 Feb 7
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering