Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator

Chulwoo Kim, In Chul Hwang, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 1 GHz DLL-based clock generator in 0.35 μm CMOS occupies 0.08 mm 2. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems, Measured peak-to-peak jitter is ±7.28 ps.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages106-107+423
EditionSUPPL.
Publication statusPublished - 2002
Externally publishedYes
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 32002 Feb 7

Other

Other2002 IEEE International Solid-State Circuits Conference
CountryUnited States
CitySan Francisco, CA
Period02/2/302/2/7

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator'. Together they form a unique fingerprint.

  • Cite this

    Kim, C., Hwang, I. C., & Kang, S. M. (2002). Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (SUPPL. ed., pp. 106-107+423)