Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator

Chulwoo Kim, In Chul Hwang, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Low-power small area±7.28 ps jitter 1 GHz delay locked loop (DLL)-based clock generator was discussed. For an open-loop VCDL, the jitter is reported to accumulate only within a single delay line. With a high-Q crystal oscillator, the DLL-based clock generator produced a clean clock signal. Delay was adjusted by controlling the supply voltage with a linear voltage regulator.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages142-143+453+123
Publication statusPublished - 2002
Externally publishedYes
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 2002 Feb 32002 Feb 7

Other

Other2002 IEEE International Solid-State Circuits Conference
CountryUnited States
CitySan Francisco, CA
Period02/2/302/2/7

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kim, C., Hwang, I. C., & Kang, S. M. (2002). Low-power small-area ±7.28ps Jitter 1GHz DLL-based clock generator. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 142-143+453+123)