Low-power small area±7.28 ps jitter 1 GHz delay locked loop (DLL)-based clock generator was discussed. For an open-loop VCDL, the jitter is reported to accumulate only within a single delay line. With a high-Q crystal oscillator, the DLL-based clock generator produced a clean clock signal. Delay was adjusted by controlling the supply voltage with a linear voltage regulator.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2002|
|Event||2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States|
Duration: 2002 Feb 3 → 2002 Feb 7
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering