A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 μm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply.
ASJC Scopus subject areas
- Electrical and Electronic Engineering