Low-power, wide-range time-to-digital converter for all digital phase-locked loops

C. H. Jeong, C. K. Kwon, H. Kim, I. C. Hwang, S. W. Kim

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 μm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply.

Original languageEnglish
Pages (from-to)96-97
Number of pages2
JournalElectronics Letters
Volume49
Issue number2
DOIs
Publication statusPublished - 2013 Jan 17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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