Low-power, wide-range time-to-digital converter for all digital phase-locked loops

C. H. Jeong; C. K. Kwon; H. Kim; I. C. Hwang; S. W. Kim

doi:10.1049/el.2012.3434

Low-power, wide-range time-to-digital converter for all digital phase-locked loops

C. H. Jeong, C. K. Kwon, H. Kim, I. C. Hwang, S. W. Kim

* Honorary professors

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 μm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply.

Original language	English
Pages (from-to)	96-97
Number of pages	2
Journal	Electronics Letters
Volume	49
Issue number	2
DOIs	https://doi.org/10.1049/el.2012.3434
Publication status	Published - 2013 Jan 17

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el.2012.3434

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AU - Hwang, I. C.

AU - Kim, S. W.

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AB - A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 μm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply.

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Low-power, wide-range time-to-digital converter for all digital phase-locked loops

Abstract

ASJC Scopus subject areas

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