Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and HighFK/Metal gate stack for Monolithic 3D integration

We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380°C. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23x10^-4Ω-cm at the lowest point of SRP) and shallow (92nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique-metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360°C, has an electron mobility comparable to the highest one reported previously [1], while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent I _on/I_off ratio (∼1.1x10³ for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400°C.