Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and HighFK/Metal gate stack for Monolithic 3D integration

Jin Hong Park, Munehiro Tada, Duygu Kuzum, Pawan Kapur, Hyun-Yong Yu, H. S Philip Wong, Krishna C. Saraswat

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Citations (Scopus)

Abstract

We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380°C. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23x10 -4Ω-cm at the lowest point of SRP) and shallow (92nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique-metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360°C, has an electron mobility comparable to the highest one reported previously [1], while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent I on/I off ratio (∼1.1x10 3 for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400°C.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
Publication statusPublished - 2008 Dec 1
Externally publishedYes
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: 2008 Dec 152008 Dec 17

Other

Other2008 IEEE International Electron Devices Meeting, IEDM 2008
CountryUnited States
CitySan Francisco, CA
Period08/12/1508/12/17

Fingerprint

CMOS
field effect transistors
Metals
Chemical activation
Doping (additives)
activation
metals
Hole mobility
Electron mobility
Crystallization
Temperature
Transistors
hole mobility
electron mobility
transistors
crystallization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Park, J. H., Tada, M., Kuzum, D., Kapur, P., Yu, H-Y., Wong, H. S. P., & Saraswat, K. C. (2008). Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and HighFK/Metal gate stack for Monolithic 3D integration. In Technical Digest - International Electron Devices Meeting, IEDM [4796702] https://doi.org/10.1109/IEDM.2008.4796702

Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and HighFK/Metal gate stack for Monolithic 3D integration. / Park, Jin Hong; Tada, Munehiro; Kuzum, Duygu; Kapur, Pawan; Yu, Hyun-Yong; Wong, H. S Philip; Saraswat, Krishna C.

Technical Digest - International Electron Devices Meeting, IEDM. 2008. 4796702.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Park, JH, Tada, M, Kuzum, D, Kapur, P, Yu, H-Y, Wong, HSP & Saraswat, KC 2008, Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and HighFK/Metal gate stack for Monolithic 3D integration. in Technical Digest - International Electron Devices Meeting, IEDM., 4796702, 2008 IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, United States, 08/12/15. https://doi.org/10.1109/IEDM.2008.4796702
Park, Jin Hong ; Tada, Munehiro ; Kuzum, Duygu ; Kapur, Pawan ; Yu, Hyun-Yong ; Wong, H. S Philip ; Saraswat, Krishna C. / Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and HighFK/Metal gate stack for Monolithic 3D integration. Technical Digest - International Electron Devices Meeting, IEDM. 2008.
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abstract = "We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380°C. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23x10 -4Ω-cm at the lowest point of SRP) and shallow (92nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique-metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360°C, has an electron mobility comparable to the highest one reported previously [1], while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent I on/I off ratio (∼1.1x10 3 for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400°C.",
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AB - We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380°C. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23x10 -4Ω-cm at the lowest point of SRP) and shallow (92nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique-metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360°C, has an electron mobility comparable to the highest one reported previously [1], while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent I on/I off ratio (∼1.1x10 3 for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400°C.

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