LPC cepstrum processor for speech recognition

In Chul Hwang, Sung Nam Kim, Young Woo Kim, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An LPC cepstrum processor for speech recognition is implemented on CMOS gate array. The processor that we designed contains a 24 bit floating-point MAC unit, which computes a correlation rapidly, the majority of operations in the algorithm. This processor has 22 register files to store temporary variables, which enable to reduce access to external memory. For the purpose of fast operations, the floating-point MAC consists of a pipeline structure with 3 stages and uses a branched postnormalization scheme proposed in this paper. Experimental results show that it takes approximately 266 us to process a frame of 20 ms at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of transistors is 55,520.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages233-236
Number of pages4
Volume4
Publication statusPublished - 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 1998 May 311998 Jun 3

Other

OtherProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)
CityMonterey, CA, USA
Period98/5/3198/6/3

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Hwang, I. C., Kim, S. N., Kim, Y. W., & Kim, S-W. (1998). LPC cepstrum processor for speech recognition. In Anon (Ed.), Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4, pp. 233-236). IEEE.