Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology

Daeik Kim, Jonghae Kim, Jean Olivier Plouchart, Choongyeun Cho, Robert Trzcinski, Sungjae Lee, Mahender Kumar, Christine Norris, Jae-Sung Rieh, Greg Freeman, David Ahlgren

Research output: Contribution to journal › Article

2 Citations (Scopus)

Abstract

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.

Original languageEnglish
Pages (from-to)520-522
Number of pages3
JournalIEEE Electron Device Letters
Volume28
Issue number6
DOIs
Publication statusPublished - 2007 Jun 1

Fingerprint

Field effect transistors
Networks (circuits)
Cutoff frequency
Silicon
Electric wiring
Statistical methods

Keywords

  • 65-nm silicon-on-insulator (SOI) CMOS
  • Circuit-level FET with wiring parasitics
  • Current gain cutoff frequency f
  • FET yield and manufacturability
  • Full 300-mm wafer statistical analysis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kim, D., Kim, J., Plouchart, J. O., Cho, C., Trzcinski, R., Lee, S., ... Ahlgren, D. (2007). Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology. IEEE Electron Device Letters, 28(6), 520-522. https://doi.org/10.1109/LED.2007.897448

Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology. / Kim, Daeik; Kim, Jonghae; Plouchart, Jean Olivier; Cho, Choongyeun; Trzcinski, Robert; Lee, Sungjae; Kumar, Mahender; Norris, Christine; Rieh, Jae-Sung; Freeman, Greg; Ahlgren, David.

In: IEEE Electron Device Letters, Vol. 28, No. 6, 01.06.2007, p. 520-522.

Research output: Contribution to journal › Article

Kim, D, Kim, J, Plouchart, JO, Cho, C, Trzcinski, R, Lee, S, Kumar, M, Norris, C, Rieh, J-S, Freeman, G & Ahlgren, D 2007, 'Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology', IEEE Electron Device Letters, vol. 28, no. 6, pp. 520-522. https://doi.org/10.1109/LED.2007.897448
Kim D, Kim J, Plouchart JO, Cho C, Trzcinski R, Lee S et al. Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology. IEEE Electron Device Letters. 2007 Jun 1;28(6):520-522. https://doi.org/10.1109/LED.2007.897448
Kim, Daeik ; Kim, Jonghae ; Plouchart, Jean Olivier ; Cho, Choongyeun ; Trzcinski, Robert ; Lee, Sungjae ; Kumar, Mahender ; Norris, Christine ; Rieh, Jae-Sung ; Freeman, Greg ; Ahlgren, David. / Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology. In: IEEE Electron Device Letters. 2007 ; Vol. 28, No. 6. pp. 520-522.
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