Abstract
This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.
Original language | English |
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Pages (from-to) | 520-522 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 28 |
Issue number | 6 |
DOIs | |
Publication status | Published - 2007 Jun |
Keywords
- 65-nm silicon-on-insulator (SOI) CMOS
- Circuit-level FET with wiring parasitics
- Current gain cutoff frequency f
- FET yield and manufacturability
- Full 300-mm wafer statistical analysis
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering