Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology

Daeik Kim; Jonghae Kim; Jean Olivier Plouchart; Choongyeun Cho; Robert Trzcinski; Sungjae Lee; Mahender Kumar; Christine Norris; Jae Sung Rieh; Greg Freeman; David Ahlgren

doi:10.1109/LED.2007.897448

Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology

Daeik Kim, Jonghae Kim, Jean Olivier Plouchart, Choongyeun Cho, Robert Trzcinski, Sungjae Lee, Mahender Kumar, Christine Norris, Jae Sung Rieh, Greg Freeman, David Ahlgren

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency f_T of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum f_T of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.

Original language	English
Pages (from-to)	520-522
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	28
Issue number	6
DOIs	https://doi.org/10.1109/LED.2007.897448
Publication status	Published - 2007 Jun

Keywords

65-nm silicon-on-insulator (SOI) CMOS
Circuit-level FET with wiring parasitics
Current gain cutoff frequency f
FET yield and manufacturability
Full 300-mm wafer statistical analysis

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2007.897448

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Manufacturable parasitic-aware circuit-level FETs in 65-nm SOI CMOS technology. / Kim, Daeik; Kim, Jonghae; Plouchart, Jean Olivier; Cho, Choongyeun; Trzcinski, Robert; Lee, Sungjae; Kumar, Mahender; Norris, Christine; Rieh, Jae Sung; Freeman, Greg; Ahlgren, David.

In: IEEE Electron Device Letters, Vol. 28, No. 6, 06.2007, p. 520-522.

Research output: Contribution to journal › Article › peer-review

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abstract = "This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm.",

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AU - Lee, Sungjae

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