TY - GEN
T1 - Memory Interfaces
T2 - Past, Present, and Future
AU - Kim, Chulwoo
AU - Lee, Hyun Woo
AU - Song, Junyoung
PY - 2016/3/1
Y1 - 2016/3/1
N2 - Over the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known "memory wall" problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM?
AB - Over the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known "memory wall" problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM?
UR - http://www.scopus.com/inward/record.url?scp=84976631779&partnerID=8YFLogxK
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U2 - 10.1109/MSSC.2016.2546659
DO - 10.1109/MSSC.2016.2546659
M3 - Article
AN - SCOPUS:84976631779
VL - 8
SP - 23
EP - 34
JO - IEEE Solid-State Circuits Magazine
JF - IEEE Solid-State Circuits Magazine
SN - 1943-0582
ER -