Memory Interfaces: Past, Present, and Future

Chulwoo Kim, Hyun Woo Lee, Junyoung Song

Research output: Contribution to specialist publicationArticle

8 Citations (Scopus)

Abstract

Over the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known "memory wall" problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM?

Original languageEnglish
Pages23-34
Number of pages12
Volume8
No.2
Specialist publicationIEEE Solid-State Circuits Magazine
DOIs
Publication statusPublished - 2016 Mar 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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