Minimizing CMT miss penalty in selective page-level address mapping table

Ronnie Mativenga, Joon Young Paik, Junghee Lee, Tae Sun Chung, Youngjae Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages152-153
Number of pages2
ISBN (Electronic)9781509036530
DOIs
Publication statusPublished - 2016 Dec 6
Externally publishedYes
Event2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 - Taipei, Taiwan, Province of China
Duration: 2016 Sep 132016 Sep 15

Publication series

NameProceedings - IEEE International Conference on Cluster Computing, ICCC
ISSN (Print)1552-5244

Conference

Conference2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
CountryTaiwan, Province of China
CityTaipei
Period16/9/1316/9/15

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Signal Processing

Fingerprint Dive into the research topics of 'Minimizing CMT miss penalty in selective page-level address mapping table'. Together they form a unique fingerprint.

  • Cite this

    Mativenga, R., Paik, J. Y., Lee, J., Chung, T. S., & Kim, Y. (2016). Minimizing CMT miss penalty in selective page-level address mapping table. In Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 (pp. 152-153). [7776497] (Proceedings - IEEE International Conference on Cluster Computing, ICCC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CLUSTER.2016.81