Abstract
Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 152-153 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781509036530 |
| DOIs | |
| Publication status | Published - 2016 Dec 6 |
| Externally published | Yes |
| Event | 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 - Taipei, Taiwan, Province of China Duration: 2016 Sep 13 → 2016 Sep 15 |
Publication series
| Name | Proceedings - IEEE International Conference on Cluster Computing, ICCC |
|---|---|
| ISSN (Print) | 1552-5244 |
Conference
| Conference | 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016 |
|---|---|
| Country | Taiwan, Province of China |
| City | Taipei |
| Period | 16/9/13 → 16/9/15 |
Fingerprint
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Signal Processing
Cite this
Minimizing CMT miss penalty in selective page-level address mapping table. / Mativenga, Ronnie; Paik, Joon Young; Lee, Junghee; Chung, Tae Sun; Kim, Youngjae.
Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 152-153 7776497 (Proceedings - IEEE International Conference on Cluster Computing, ICCC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Minimizing CMT miss penalty in selective page-level address mapping table
AU - Mativenga, Ronnie
AU - Paik, Joon Young
AU - Lee, Junghee
AU - Chung, Tae Sun
AU - Kim, Youngjae
PY - 2016/12/6
Y1 - 2016/12/6
N2 - Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.
AB - Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.
UR - http://www.scopus.com/inward/record.url?scp=85013156584&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85013156584&partnerID=8YFLogxK
U2 - 10.1109/CLUSTER.2016.81
DO - 10.1109/CLUSTER.2016.81
M3 - Conference contribution
AN - SCOPUS:85013156584
T3 - Proceedings - IEEE International Conference on Cluster Computing, ICCC
SP - 152
EP - 153
BT - Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
PB - Institute of Electrical and Electronics Engineers Inc.
ER -