TY - GEN
T1 - Minimizing CMT miss penalty in selective page-level address mapping table
AU - Mativenga, Ronnie
AU - Paik, Joon Young
AU - Lee, Junghee
AU - Chung, Tae Sun
AU - Kim, Youngjae
N1 - Funding Information:
This work was supported by the Institute for Information & communications Technology Promotion (IITP) grant (No. R0190-15-2012) and National Research Foundation of Korea (NRF) grant (No. 2015R1C1A1A0152105), and partially by the Ajou University research fund.
Publisher Copyright:
© 2016 IEEE.
PY - 2016/12/6
Y1 - 2016/12/6
N2 - Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.
AB - Flash Translation Layer (FTL) performs virtual-tophysical address translations and hides the erase-before-write characteristics of Flash. Pure page mapped FTL, which maintains page-level address mappings, is known as the most efficient FTL. However, its huge SRAM requirement to load the entire mapping table limited adoption of its use. In order to reduce SRAM space utilization while maintaining comparable performance, we can selectively cache page-level address mappings into a small SRAM. However, the performance of this approach is limited by miss ratio of cached mapping table (CMT) on SRAM. In this paper, we propose a replica approach of the page-mapped FTL on flash, called Replica to minimize the performance penalty of CMT miss.
UR - http://www.scopus.com/inward/record.url?scp=85013156584&partnerID=8YFLogxK
U2 - 10.1109/CLUSTER.2016.81
DO - 10.1109/CLUSTER.2016.81
M3 - Conference contribution
AN - SCOPUS:85013156584
T3 - Proceedings - IEEE International Conference on Cluster Computing, ICCC
SP - 152
EP - 153
BT - Proceedings - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Conference on Cluster Computing, CLUSTER 2016
Y2 - 13 September 2016 through 15 September 2016
ER -