Minimizing the directory size for large-scale shared-memory multiprocessors

Jinseok Kong, Pen Chung Yew, Kyung Ho Lee

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cn log2 n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.

Original languageEnglish
Pages (from-to)2533-2542
Number of pages10
JournalIEICE Transactions on Information and Systems
VolumeE88-D
Issue number11
DOIs
Publication statusPublished - 2005 Nov 1
Externally publishedYes

Fingerprint

Physical addresses
Cache memory
Hardware
Data storage equipment

Keywords

  • Cache coherence
  • Directory protocol
  • Multiprocessor
  • Shared memory architecture

ASJC Scopus subject areas

  • Information Systems
  • Computer Graphics and Computer-Aided Design
  • Software

Cite this

Minimizing the directory size for large-scale shared-memory multiprocessors. / Kong, Jinseok; Yew, Pen Chung; Lee, Kyung Ho.

In: IEICE Transactions on Information and Systems, Vol. E88-D, No. 11, 01.11.2005, p. 2533-2542.

Research output: Contribution to journalArticle

@article{7cdf5eb65736480d884470e944b3afd4,
title = "Minimizing the directory size for large-scale shared-memory multiprocessors",
abstract = "Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cn log2 n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.",
keywords = "Cache coherence, Directory protocol, Multiprocessor, Shared memory architecture",
author = "Jinseok Kong and Yew, {Pen Chung} and Lee, {Kyung Ho}",
year = "2005",
month = "11",
day = "1",
doi = "10.1093/ietisy/e88-d.11.2533",
language = "English",
volume = "E88-D",
pages = "2533--2542",
journal = "IEICE Transactions on Information and Systems",
issn = "0916-8532",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "11",

}

TY - JOUR

T1 - Minimizing the directory size for large-scale shared-memory multiprocessors

AU - Kong, Jinseok

AU - Yew, Pen Chung

AU - Lee, Kyung Ho

PY - 2005/11/1

Y1 - 2005/11/1

N2 - Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cn log2 n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.

AB - Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cn log2 n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.

KW - Cache coherence

KW - Directory protocol

KW - Multiprocessor

KW - Shared memory architecture

UR - http://www.scopus.com/inward/record.url?scp=29144459927&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=29144459927&partnerID=8YFLogxK

U2 - 10.1093/ietisy/e88-d.11.2533

DO - 10.1093/ietisy/e88-d.11.2533

M3 - Article

AN - SCOPUS:29144459927

VL - E88-D

SP - 2533

EP - 2542

JO - IEICE Transactions on Information and Systems

JF - IEICE Transactions on Information and Systems

SN - 0916-8532

IS - 11

ER -