Multiple bit operation of MFISFET with Pt/SrBi 2Ta 2O 9/Y 2O 3/Si gate structure

Sun Il Shim, Young Suk Kwon, Ik Soo Kim, Seong Il Kim, Yong Tae Kim, Jung ho Park

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

A single transistor type ferroelectric memory with multiple bit operation was presented. This cell has a metal ferroelectric insulator semiconductor field effect transistor structure. Y 2O 3 thin film was used as a buffer insulating layer to improve the memory characteristics and SrBi 2Ta 2O 9 was used as a ferroelectric gate material. The multi-level characteristics of four levels with one order of drain current difference were measured according to the writing voltage step of two volt. This multi-level memory cell enables to increase the density of memory in the same space and lower the cost.

Original languageEnglish
Title of host publicationIntegrated Ferroelectrics
Pages203-211
Number of pages9
Volume65
DOIs
Publication statusPublished - 2004

    Fingerprint

Keywords

  • Ferroelectric
  • FRAM
  • MFISFET
  • Multi-level
  • SBT

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

Cite this

Shim, S. I., Kwon, Y. S., Kim, I. S., Kim, S. I., Kim, Y. T., & Park, J. H. (2004). Multiple bit operation of MFISFET with Pt/SrBi 2Ta 2O 9/Y 2O 3/Si gate structure In Integrated Ferroelectrics (Vol. 65, pp. 203-211) https://doi.org/10.1080/10584580490893079