Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0 V and V _dd with a high voltage gain of ∼29 and a sharp transition of 0.28 V at V _dd = 3 V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for V _dd = 3 V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits.