Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

M. Lee, Y. Jeon, J. C. Jung, S. M. Koo, Sangsig Kim

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0 V and V dd with a high voltage gain of ∼29 and a sharp transition of 0.28 V at V dd = 3 V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for V dd = 3 V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits.

Original languageEnglish
Article number253506
JournalApplied Physics Letters
Volume100
Issue number25
DOIs
Publication statusPublished - 2012 Jun 18

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logic
tunnels
nanowires
transistors
silicon
field effect transistors
logic circuits
electric potential
high voltages
leakage
plastics
retarding
conduction
fabrication
output
simulation

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications. / Lee, M.; Jeon, Y.; Jung, J. C.; Koo, S. M.; Kim, Sangsig.

In: Applied Physics Letters, Vol. 100, No. 25, 253506, 18.06.2012.

Research output: Contribution to journalArticle

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