TY - JOUR
T1 - Near threshold voltage digital PLL using low voltage optimised blocks for AR display system
AU - Jun, Jaehun
AU - Lee, Sangsu
AU - Kim, Chulwoo
N1 - Funding Information:
This work was supported by the IT R&D program of MOTIE/ KEIT. [10052716, Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for smart sensor SoC].
Publisher Copyright:
© The Institution of Engineering and Technology 2019
PY - 2020/3/1
Y1 - 2020/3/1
N2 - In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.
AB - In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.
UR - http://www.scopus.com/inward/record.url?scp=85080108233&partnerID=8YFLogxK
U2 - 10.1049/iet-cds.2018.5468
DO - 10.1049/iet-cds.2018.5468
M3 - Review article
AN - SCOPUS:85080108233
VL - 14
SP - 155
EP - 158
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
SN - 1751-858X
IS - 2
ER -