New architecture for the fast Viterbi algorithm

Inkyu Lee, Jeff L. Sonntag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

A novel architecture design to speed up the Viterbi algorithm is proposed. By doubling the number of states in the trellis, the serial operation of a traditional Add-Compare-Select (ACS) unit is transformed into a parallel operation, thus achieving a substantial speed increase. The use of the proposed architecture would increase the speed by 33% at the expense of a faily modest increase in area, thus removing the Viterbi detector/decoder from the worst case speed bottleneck path in most high-speed applications. A simple example is shown to illustrate the proposed algorithm in Maximum Likelihood Sequence Detector.

Original languageEnglish
Title of host publicationConference Record / IEEE Global Telecommunications Conference
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages1664-1668
Number of pages5
Volume3
Publication statusPublished - 2000 Dec 1
Externally publishedYes

Fingerprint

Viterbi algorithm
Detectors
Maximum likelihood
speed

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change

Cite this

Lee, I., & Sonntag, J. L. (2000). New architecture for the fast Viterbi algorithm. In Conference Record / IEEE Global Telecommunications Conference (Vol. 3, pp. 1664-1668). Piscataway, NJ, United States: IEEE.

New architecture for the fast Viterbi algorithm. / Lee, Inkyu; Sonntag, Jeff L.

Conference Record / IEEE Global Telecommunications Conference. Vol. 3 Piscataway, NJ, United States : IEEE, 2000. p. 1664-1668.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, I & Sonntag, JL 2000, New architecture for the fast Viterbi algorithm. in Conference Record / IEEE Global Telecommunications Conference. vol. 3, IEEE, Piscataway, NJ, United States, pp. 1664-1668.
Lee I, Sonntag JL. New architecture for the fast Viterbi algorithm. In Conference Record / IEEE Global Telecommunications Conference. Vol. 3. Piscataway, NJ, United States: IEEE. 2000. p. 1664-1668
Lee, Inkyu ; Sonntag, Jeff L. / New architecture for the fast Viterbi algorithm. Conference Record / IEEE Global Telecommunications Conference. Vol. 3 Piscataway, NJ, United States : IEEE, 2000. pp. 1664-1668
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