Abstract
In this paper, we present a fast motion estimation algorithm based on bit-plane matching and its hardware implementation. The proposed algorithm performs motion estimation using 1-bit planes that are extracted from a video sequence. The proposed algorithm can be realized using only simple Boolean functions and makes a cheaper and faster implementation possible, while maintaining the accuracy of motion estimation. The proposed motion estimator has been implemented in FPGA and operates fast enough to handle real time video applications such as H.261/263 and MPEG-1/2.
| Original language | English |
|---|---|
| Title of host publication | IEEE Region 10 Annual International Conference, Proceedings/TENCON |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 848-851 |
| Number of pages | 4 |
| Volume | 2 |
| ISBN (Electronic) | 0780357396, 9780780357396 |
| DOIs | |
| Publication status | Published - 1999 Jan 1 |
| Event | 1999 IEEE Region 10 Conference, TENCON 1999 - Cheju Island, Korea, Republic of Duration: 1999 Sep 15 → 1999 Sep 17 |
Other
| Other | 1999 IEEE Region 10 Conference, TENCON 1999 |
|---|---|
| Country | Korea, Republic of |
| City | Cheju Island |
| Period | 99/9/15 → 99/9/17 |
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ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering
Cite this
New motion estimation algorithm based on bit-plane matching and its VLSI implementation. / Ko, Young Ki; Kim, Hyun Gyu; Lee, Jong Wook; Kim, Young Ro; Oh, Hyeong Cheol; Ko, Sung-Jea.
IEEE Region 10 Annual International Conference, Proceedings/TENCON. Vol. 2 Institute of Electrical and Electronics Engineers Inc., 1999. p. 848-851.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - New motion estimation algorithm based on bit-plane matching and its VLSI implementation
AU - Ko, Young Ki
AU - Kim, Hyun Gyu
AU - Lee, Jong Wook
AU - Kim, Young Ro
AU - Oh, Hyeong Cheol
AU - Ko, Sung-Jea
PY - 1999/1/1
Y1 - 1999/1/1
N2 - In this paper, we present a fast motion estimation algorithm based on bit-plane matching and its hardware implementation. The proposed algorithm performs motion estimation using 1-bit planes that are extracted from a video sequence. The proposed algorithm can be realized using only simple Boolean functions and makes a cheaper and faster implementation possible, while maintaining the accuracy of motion estimation. The proposed motion estimator has been implemented in FPGA and operates fast enough to handle real time video applications such as H.261/263 and MPEG-1/2.
AB - In this paper, we present a fast motion estimation algorithm based on bit-plane matching and its hardware implementation. The proposed algorithm performs motion estimation using 1-bit planes that are extracted from a video sequence. The proposed algorithm can be realized using only simple Boolean functions and makes a cheaper and faster implementation possible, while maintaining the accuracy of motion estimation. The proposed motion estimator has been implemented in FPGA and operates fast enough to handle real time video applications such as H.261/263 and MPEG-1/2.
UR - http://www.scopus.com/inward/record.url?scp=84992666580&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84992666580&partnerID=8YFLogxK
U2 - 10.1109/TENCON.1999.818551
DO - 10.1109/TENCON.1999.818551
M3 - Conference contribution
VL - 2
SP - 848
EP - 851
BT - IEEE Region 10 Annual International Conference, Proceedings/TENCON
PB - Institute of Electrical and Electronics Engineers Inc.
ER -