New transformation method to generate optimized DO loop from FORALL construct

Mi Soon Koo, Sung Soon Park, Hyun Gyoo Yook, Myong Soon Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Data parallel language was suggested to solve programming problems of distributed memory machines in terms of programming language. Among data parallel languages, HPF is a standard data parallel language across a variety of high-performance architectures. And most HPF compilers are source-to-source translators because they can be easily implemented. However, these source-to-source compilers produce significant amount of ineffective codes. In particular, FORALL construct is converted into several DO loops, so its loop overhead is increased. Therefore, we propose some techniques for converting FORALL construct to optimized DO loop. For this, we define and use relation distance vector which can represent both data dependence information and flow information. Then we evaluate and analyze execution time for the codes converted by our method and by PARADIGM method.

Original languageEnglish
Title of host publicationAizu International Symposium on Parallel Algorithms/Architecture Synthesis
EditorsN. Mirenkov, Q.P. Gu, S. Peng, S. Sedukhin
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages240-247
Number of pages8
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis - Fukushima, Jpn
Duration: 1997 Mar 171997 Mar 21

Other

OtherProceedings of the 1997 2nd Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
CityFukushima, Jpn
Period97/3/1797/3/21

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ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Koo, M. S., Park, S. S., Yook, H. G., & Park, M. S. (1997). New transformation method to generate optimized DO loop from FORALL construct. In N. Mirenkov, Q. P. Gu, S. Peng, & S. Sedukhin (Eds.), Aizu International Symposium on Parallel Algorithms/Architecture Synthesis (pp. 240-247). Piscataway, NJ, United States: IEEE.