NMOS Energy Recovery Logic

Chulwoo Kim, Seung Moon Yoo, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping. NERL shows full output voltage swing, insensitivity to output load capacitance, less dependency on power-clock frequency and complementary outputs for balanced capacitance load to power-clock. We have designed an 8-bit CLA and inverter chain using 0.6 μm CMOS technology and verified that NERL saves energy over ECRL by 2 to 3 times.

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages310-313
Number of pages4
ISBN (Print)0769501044
Publication statusPublished - 1999
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: 1999 Mar 41999 Mar 6

Publication series

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395

Other

OtherProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period99/3/499/3/6

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kim, C., Yoo, S. M., & Kang, S. M. (1999). NMOS Energy Recovery Logic. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 310-313). (Proceedings of the IEEE Great Lakes Symposium on VLSI). IEEE.