Noise-aware domino logic design for deep submicron technology

Seok Soo Yoon, Seok Ryong Yoon, Soo-Won Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18um CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.

Original languageEnglish
Title of host publication2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages277-280
Number of pages4
ISBN (Print)0780377494, 9780780377493
DOIs
Publication statusPublished - 2003
EventIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong
Duration: 2003 Dec 162003 Dec 18

Other

OtherIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
CountryHong Kong
CityTsimshatsui, Kowloon
Period03/12/1603/12/18

Fingerprint

Logic design
Logic gates
Textbooks
Transistors
Networks (circuits)
Electric potential
Logic Synthesis

Keywords

  • Charge sharing problem
  • Deep submicron technology
  • Domino logic
  • Keeper size
  • Noise
  • Power X delay
  • Split-path

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yoon, S. S., Yoon, S. R., Kim, S-W., & Kim, C. (2003). Noise-aware domino logic design for deep submicron technology. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 277-280). [1283531] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283531

Noise-aware domino logic design for deep submicron technology. / Yoon, Seok Soo; Yoon, Seok Ryong; Kim, Soo-Won; Kim, Chulwoo.

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 277-280 1283531.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoon, SS, Yoon, SR, Kim, S-W & Kim, C 2003, Noise-aware domino logic design for deep submicron technology. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283531, Institute of Electrical and Electronics Engineers Inc., pp. 277-280, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 03/12/16. https://doi.org/10.1109/EDSSC.2003.1283531
Yoon SS, Yoon SR, Kim S-W, Kim C. Noise-aware domino logic design for deep submicron technology. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 277-280. 1283531 https://doi.org/10.1109/EDSSC.2003.1283531
Yoon, Seok Soo ; Yoon, Seok Ryong ; Kim, Soo-Won ; Kim, Chulwoo. / Noise-aware domino logic design for deep submicron technology. 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 277-280
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