Noise-aware domino logic design for deep submicron technology

Seok Soo Yoon; Seok Ryong Yoon; Soo Won Kim; Chulwoo Kim

doi:10.1109/EDSSC.2003.1283531

Noise-aware domino logic design for deep submicron technology

Seok Soo Yoon, Seok Ryong Yoon, Soo Won Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18um CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.

Original language	English
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	277-280
Number of pages	4
ISBN (Electronic)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283531
Publication status	Published - 2003
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 2003 Dec 16 → 2003 Dec 18

Publication series

Name	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country	Hong Kong
City	Tsimshatsui, Kowloon
Period	03/12/16 → 03/12/18

Keywords

Charge sharing problem
Deep submicron technology
Domino logic
Keeper size
Noise
Power X delay
Split-path

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2003.1283531

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Yoon, S. S., Yoon, S. R., Kim, S. W., & Kim, C. (2003). Noise-aware domino logic design for deep submicron technology. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 277-280). [1283531] (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283531

Noise-aware domino logic design for deep submicron technology. / Yoon, Seok Soo; Yoon, Seok Ryong; Kim, Soo Won; Kim, Chulwoo.

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 277-280 1283531 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yoon, SS, Yoon, SR, Kim, SW & Kim, C 2003, Noise-aware domino logic design for deep submicron technology. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283531, 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 277-280, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 03/12/16. https://doi.org/10.1109/EDSSC.2003.1283531

Yoon SS, Yoon SR, Kim SW, Kim C. Noise-aware domino logic design for deep submicron technology. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 277-280. 1283531. (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). https://doi.org/10.1109/EDSSC.2003.1283531

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title = "Noise-aware domino logic design for deep submicron technology",

abstract = "In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18um CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.",

keywords = "Charge sharing problem, Deep submicron technology, Domino logic, Keeper size, Noise, Power X delay, Split-path",

author = "Yoon, {Seok Soo} and Yoon, {Seok Ryong} and Kim, {Soo Won} and Chulwoo Kim",

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series = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

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N2 - In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18um CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.

AB - In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18um CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.

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Noise-aware domino logic design for deep submicron technology

Abstract

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Keywords

ASJC Scopus subject areas

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