Abstract
In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18um CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.
Original language | English |
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Title of host publication | 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 277-280 |
Number of pages | 4 |
ISBN (Print) | 0780377494, 9780780377493 |
DOIs | |
Publication status | Published - 2003 |
Event | IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 2003 Dec 16 → 2003 Dec 18 |
Other
Other | IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 |
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Country | Hong Kong |
City | Tsimshatsui, Kowloon |
Period | 03/12/16 → 03/12/18 |
Keywords
- Charge sharing problem
- Deep submicron technology
- Domino logic
- Keeper size
- Noise
- Power X delay
- Split-path
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering