Noise-aware split-path domino logic and its clock delaying scheme

Dongkyu Park, Seoksoo Yoon, Inhwa Jung, Chulwoo Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

Original languageEnglish
Pages (from-to)139-154
Number of pages16
JournalJournal of Circuits, Systems and Computers
Volume16
Issue number1
DOIs
Publication statusPublished - 2007 Feb

Keywords

  • Adders
  • Charge-sharing noise
  • Split-path domino logic circuit

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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