Noise-aware split-path domino logic and its clock delaying scheme

Dongkyu Park, Seoksoo Yoon, Inhwa Jung, Chulwoo Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

Original languageEnglish
Pages (from-to)139-154
Number of pages16
JournalJournal of Circuits, Systems and Computers
Volume16
Issue number1
DOIs
Publication statusPublished - 2007 Feb 1

Fingerprint

Logic circuits
Clocks
Adders
Networks (circuits)
Threshold voltage
Transistors
Electric power utilization
Electric potential
Temperature

Keywords

  • Adders
  • Charge-sharing noise
  • Split-path domino logic circuit

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Noise-aware split-path domino logic and its clock delaying scheme. / Park, Dongkyu; Yoon, Seoksoo; Jung, Inhwa; Kim, Chulwoo.

In: Journal of Circuits, Systems and Computers, Vol. 16, No. 1, 01.02.2007, p. 139-154.

Research output: Contribution to journalArticle

Park, Dongkyu ; Yoon, Seoksoo ; Jung, Inhwa ; Kim, Chulwoo. / Noise-aware split-path domino logic and its clock delaying scheme. In: Journal of Circuits, Systems and Computers. 2007 ; Vol. 16, No. 1. pp. 139-154.
@article{1f25d58aed4647bfbab20417b46133be,
title = "Noise-aware split-path domino logic and its clock delaying scheme",
abstract = "This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15{\%} compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.",
keywords = "Adders, Charge-sharing noise, Split-path domino logic circuit",
author = "Dongkyu Park and Seoksoo Yoon and Inhwa Jung and Chulwoo Kim",
year = "2007",
month = "2",
day = "1",
doi = "10.1142/S0218126607003563",
language = "English",
volume = "16",
pages = "139--154",
journal = "Journal of Circuits, Systems and Computers",
issn = "0218-1266",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "1",

}

TY - JOUR

T1 - Noise-aware split-path domino logic and its clock delaying scheme

AU - Park, Dongkyu

AU - Yoon, Seoksoo

AU - Jung, Inhwa

AU - Kim, Chulwoo

PY - 2007/2/1

Y1 - 2007/2/1

N2 - This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

AB - This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

KW - Adders

KW - Charge-sharing noise

KW - Split-path domino logic circuit

UR - http://www.scopus.com/inward/record.url?scp=34249309624&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34249309624&partnerID=8YFLogxK

U2 - 10.1142/S0218126607003563

DO - 10.1142/S0218126607003563

M3 - Article

VL - 16

SP - 139

EP - 154

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

SN - 0218-1266

IS - 1

ER -