Abstract
This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.
| Original language | English |
|---|---|
| Pages (from-to) | 139-154 |
| Number of pages | 16 |
| Journal | Journal of Circuits, Systems and Computers |
| Volume | 16 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2007 Feb 1 |
Fingerprint
Keywords
- Adders
- Charge-sharing noise
- Split-path domino logic circuit
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
Cite this
Noise-aware split-path domino logic and its clock delaying scheme. / Park, Dongkyu; Yoon, Seoksoo; Jung, Inhwa; Kim, Chulwoo.
In: Journal of Circuits, Systems and Computers, Vol. 16, No. 1, 01.02.2007, p. 139-154.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Noise-aware split-path domino logic and its clock delaying scheme
AU - Park, Dongkyu
AU - Yoon, Seoksoo
AU - Jung, Inhwa
AU - Kim, Chulwoo
PY - 2007/2/1
Y1 - 2007/2/1
N2 - This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.
AB - This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han-Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.
KW - Adders
KW - Charge-sharing noise
KW - Split-path domino logic circuit
UR - http://www.scopus.com/inward/record.url?scp=34249309624&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34249309624&partnerID=8YFLogxK
U2 - 10.1142/S0218126607003563
DO - 10.1142/S0218126607003563
M3 - Article
VL - 16
SP - 139
EP - 154
JO - Journal of Circuits, Systems and Computers
JF - Journal of Circuits, Systems and Computers
SN - 0218-1266
IS - 1
ER -