We demonstrate the effect of SF6 plasma passivation with a ZnO interlayer in a metal-interlayersemiconductor (MIS) structure to reduce source/drain (S/D) contact resistance. The interface trap states and the metalinduced gap states causing the Fermi-level pinning problem are effectively alleviated by passivating the GaAs surface with SF6 plasma treatment and inserting a thin ZnO interlayer, respectively. Specific contact resistivity exhibits ∼104× reduction when the GaAs surface is treated with SF6 plasma, followed by ZnO interlayer deposition, compared with the Ti/n-GaAs (∼2×1018 cm-3) S/D contact. This result proposes the promising non-alloyed S/D ohmic contact for III-V semiconductor-based transistors.
- Contact resistance
- Fermi-level unpinning
- Gallium arsenide
- SF6 plasma
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering