Abstract
In this brief, we present a novel folding technique for high-speed and low-cost Bose-Chaudhuri-Hocquenghem (BCH) decoders. In the conventional BCH decoder, the critical path lies on the Galois-field (GF) multiplier of the key equation solver, where the speedup of the critical path is very difficult due to a significant area increase. In the proposed work, the regularly structured GF multiplier is introduced to be efficiently folded to reduce the complexity and the critical delay. Moreover, the conventional global folding scheme can be applied to further reduce the hardware costs. The implementation results show that the proposed folding scheme enhances the area efficiency by 1.73 and 1.9 times in the Digital Video Broadcasting-Satellite-Second Generation system and the storage controller, respectively.
| Original language | English |
|---|---|
| Article number | 7527672 |
| Pages (from-to) | 535-539 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 64 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2017 May 1 |
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Keywords
- Bose-Chaudhuri-Hocquenghem (BCH) decoder
- folded Galois-field (GF) multiplier
- hybrid folded key equation solver (KES)
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Novel folded-KES architecture for high-speed and area-efficient BCH decoders. / Park, Byeonggil; An, Seungyong; Park, Jongsun; Lee, Youngjoo.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 5, 7527672, 01.05.2017, p. 535-539.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Novel folded-KES architecture for high-speed and area-efficient BCH decoders
AU - Park, Byeonggil
AU - An, Seungyong
AU - Park, Jongsun
AU - Lee, Youngjoo
PY - 2017/5/1
Y1 - 2017/5/1
N2 - In this brief, we present a novel folding technique for high-speed and low-cost Bose-Chaudhuri-Hocquenghem (BCH) decoders. In the conventional BCH decoder, the critical path lies on the Galois-field (GF) multiplier of the key equation solver, where the speedup of the critical path is very difficult due to a significant area increase. In the proposed work, the regularly structured GF multiplier is introduced to be efficiently folded to reduce the complexity and the critical delay. Moreover, the conventional global folding scheme can be applied to further reduce the hardware costs. The implementation results show that the proposed folding scheme enhances the area efficiency by 1.73 and 1.9 times in the Digital Video Broadcasting-Satellite-Second Generation system and the storage controller, respectively.
AB - In this brief, we present a novel folding technique for high-speed and low-cost Bose-Chaudhuri-Hocquenghem (BCH) decoders. In the conventional BCH decoder, the critical path lies on the Galois-field (GF) multiplier of the key equation solver, where the speedup of the critical path is very difficult due to a significant area increase. In the proposed work, the regularly structured GF multiplier is introduced to be efficiently folded to reduce the complexity and the critical delay. Moreover, the conventional global folding scheme can be applied to further reduce the hardware costs. The implementation results show that the proposed folding scheme enhances the area efficiency by 1.73 and 1.9 times in the Digital Video Broadcasting-Satellite-Second Generation system and the storage controller, respectively.
KW - Bose-Chaudhuri-Hocquenghem (BCH) decoder
KW - folded Galois-field (GF) multiplier
KW - hybrid folded key equation solver (KES)
UR - http://www.scopus.com/inward/record.url?scp=85018865680&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85018865680&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2016.2596777
DO - 10.1109/TCSII.2016.2596777
M3 - Article
VL - 64
SP - 535
EP - 539
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 5
M1 - 7527672
ER -