Novel folded-KES architecture for high-speed and area-efficient BCH decoders

Byeonggil Park, Seungyong An, Jongsun Park, Youngjoo Lee

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

In this brief, we present a novel folding technique for high-speed and low-cost Bose-Chaudhuri-Hocquenghem (BCH) decoders. In the conventional BCH decoder, the critical path lies on the Galois-field (GF) multiplier of the key equation solver, where the speedup of the critical path is very difficult due to a significant area increase. In the proposed work, the regularly structured GF multiplier is introduced to be efficiently folded to reduce the complexity and the critical delay. Moreover, the conventional global folding scheme can be applied to further reduce the hardware costs. The implementation results show that the proposed folding scheme enhances the area efficiency by 1.73 and 1.9 times in the Digital Video Broadcasting-Satellite-Second Generation system and the storage controller, respectively.

Original languageEnglish
Article number7527672
Pages (from-to)535-539
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume64
Issue number5
DOIs
Publication statusPublished - 2017 May 1

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Keywords

  • Bose-Chaudhuri-Hocquenghem (BCH) decoder
  • folded Galois-field (GF) multiplier
  • hybrid folded key equation solver (KES)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Novel folded-KES architecture for high-speed and area-efficient BCH decoders. / Park, Byeonggil; An, Seungyong; Park, Jongsun; Lee, Youngjoo.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 5, 7527672, 01.05.2017, p. 535-539.

Research output: Contribution to journalArticle

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