This letter proposes a new moving-Average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs.
- Digital phase-locked loop (DPLL)
- moving average
- optimal memory size
ASJC Scopus subject areas
- Signal Processing
- Applied Mathematics
- Electrical and Electronic Engineering