Parallel configuration of oscillator for strong harmonics suppression and frequency doubler

K. J. Lee, C. W. Jang, J. P. Ko, Y. S. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are presented. In the oscillator design, as the fundamental signal is extracted between the dielectric resonator (DR) filter and the gate of the active device, the undesired harmonics at the output of the oscillator are remarkably suppressed. The fundamental signal of the oscillator directly feeds to the frequency doubler without an additional band pass filter to suppress spurious harmonics. The second harmonic suppression of -47.7 dBc at the single oscillator output and the fundamental suppression of -37.5 dBc at the frequency doubler output are achieved, respectably.

Original languageEnglish
Title of host publicationAPMC 2005
Subtitle of host publicationAsia-Pacific Microwave Conference Proceedings 2005
DOIs
Publication statusPublished - 2005
EventAPMC 2005: Asia-Pacific Microwave Conference 2005 - Suzhou, China
Duration: 2005 Dec 42005 Dec 7

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC
Volume5

Other

OtherAPMC 2005: Asia-Pacific Microwave Conference 2005
CountryChina
CitySuzhou
Period05/12/405/12/7

ASJC Scopus subject areas

  • Engineering(all)

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    Lee, K. J., Jang, C. W., Ko, J. P., & Kim, Y. S. (2005). Parallel configuration of oscillator for strong harmonics suppression and frequency doubler. In APMC 2005: Asia-Pacific Microwave Conference Proceedings 2005 [1607068] (Asia-Pacific Microwave Conference Proceedings, APMC; Vol. 5). https://doi.org/10.1109/APMC.2005.1607068