Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

Chulwoo Kim, Seong Ook Jung, Kwang Hyun Baek, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Volume1
Publication statusPublished - 2000
Externally publishedYes
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: 2000 May 282000 May 31

Other

OtherProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems
CityGeneva, Switz
Period00/5/2800/5/31

Fingerprint

Transistors
Adders
Clocks
Electric potential
Logic Synthesis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, C., Jung, S. O., Baek, K. H., & Kang, S. M. (2000). Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1). IEEE.

Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic. / Kim, Chulwoo; Jung, Seong Ook; Baek, Kwang Hyun; Kang, Sung Mo.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1 IEEE, 2000.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, C, Jung, SO, Baek, KH & Kang, SM 2000, Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 1, IEEE, Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems, Geneva, Switz, 00/5/28.
Kim C, Jung SO, Baek KH, Kang SM. Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1. IEEE. 2000
Kim, Chulwoo ; Jung, Seong Ook ; Baek, Kwang Hyun ; Kang, Sung Mo. / Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1 IEEE, 2000.
@inproceedings{5184be35ec0c4d2e9fae7da0f6582f4c,
title = "Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic",
abstract = "In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27{\%} and power×delay by 20-37{\%}.",
author = "Chulwoo Kim and Jung, {Seong Ook} and Baek, {Kwang Hyun} and Kang, {Sung Mo}",
year = "2000",
language = "English",
volume = "1",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "IEEE",

}

TY - GEN

T1 - Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

AU - Kim, Chulwoo

AU - Jung, Seong Ook

AU - Baek, Kwang Hyun

AU - Kang, Sung Mo

PY - 2000

Y1 - 2000

N2 - In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

AB - In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

UR - http://www.scopus.com/inward/record.url?scp=0033698194&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033698194&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0033698194

VL - 1

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -