Peak channel temperature of graphene-based transistors

Geunwoo Ko, Younghun Jung, Ji Hyun Kim

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

In this study, graphene was mechanically deposited on SiO 2/Si substrate, followed by ohmic metallization using electron-beam lithography. Finite element analysis was employed to characterize the operating temperature of graphene-based devices using the experimentally determined currentvoltage data. The temperature of the hottest spot where the underlying SiO 2 layer was 300 nm thick was elevated up to about 70 °C at a 10 mW dissipated power. However, the operating temperature dropped to about 50 °C when the 300 nm thick SiO 2 layer was replaced with a 20 nm thick SiO 2 layer. Thermal management is very critical in the reliability of graphene-based high speed electronic devices because the high operating temperature can degrade the device performance.

Original languageEnglish
Pages (from-to)4889-4892
Number of pages4
JournalJournal of Nanoscience and Nanotechnology
Volume10
Issue number8
DOIs
Publication statusPublished - 2010 Aug 1

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Graphite
operating temperature
Graphene
graphene
Transistors
transistors
Equipment and Supplies
Temperature
Hot Temperature
Finite Element Analysis
temperature
Electron beam lithography
lithography
Metallizing
high speed
Temperature control
electron beams
Electrons
electronics
Finite element method

Keywords

  • Channel temperature
  • Graphene
  • Transistor

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Chemistry(all)
  • Materials Science(all)
  • Bioengineering
  • Biomedical Engineering

Cite this

Peak channel temperature of graphene-based transistors. / Ko, Geunwoo; Jung, Younghun; Kim, Ji Hyun.

In: Journal of Nanoscience and Nanotechnology, Vol. 10, No. 8, 01.08.2010, p. 4889-4892.

Research output: Contribution to journalArticle

Ko, Geunwoo ; Jung, Younghun ; Kim, Ji Hyun. / Peak channel temperature of graphene-based transistors. In: Journal of Nanoscience and Nanotechnology. 2010 ; Vol. 10, No. 8. pp. 4889-4892.
@article{be81909087b24d369c5b18ee777f299a,
title = "Peak channel temperature of graphene-based transistors",
abstract = "In this study, graphene was mechanically deposited on SiO 2/Si substrate, followed by ohmic metallization using electron-beam lithography. Finite element analysis was employed to characterize the operating temperature of graphene-based devices using the experimentally determined currentvoltage data. The temperature of the hottest spot where the underlying SiO 2 layer was 300 nm thick was elevated up to about 70 °C at a 10 mW dissipated power. However, the operating temperature dropped to about 50 °C when the 300 nm thick SiO 2 layer was replaced with a 20 nm thick SiO 2 layer. Thermal management is very critical in the reliability of graphene-based high speed electronic devices because the high operating temperature can degrade the device performance.",
keywords = "Channel temperature, Graphene, Transistor",
author = "Geunwoo Ko and Younghun Jung and Kim, {Ji Hyun}",
year = "2010",
month = "8",
day = "1",
doi = "10.1166/jnn.2010.2414",
language = "English",
volume = "10",
pages = "4889--4892",
journal = "Journal of Nanoscience and Nanotechnology",
issn = "1533-4880",
publisher = "American Scientific Publishers",
number = "8",

}

TY - JOUR

T1 - Peak channel temperature of graphene-based transistors

AU - Ko, Geunwoo

AU - Jung, Younghun

AU - Kim, Ji Hyun

PY - 2010/8/1

Y1 - 2010/8/1

N2 - In this study, graphene was mechanically deposited on SiO 2/Si substrate, followed by ohmic metallization using electron-beam lithography. Finite element analysis was employed to characterize the operating temperature of graphene-based devices using the experimentally determined currentvoltage data. The temperature of the hottest spot where the underlying SiO 2 layer was 300 nm thick was elevated up to about 70 °C at a 10 mW dissipated power. However, the operating temperature dropped to about 50 °C when the 300 nm thick SiO 2 layer was replaced with a 20 nm thick SiO 2 layer. Thermal management is very critical in the reliability of graphene-based high speed electronic devices because the high operating temperature can degrade the device performance.

AB - In this study, graphene was mechanically deposited on SiO 2/Si substrate, followed by ohmic metallization using electron-beam lithography. Finite element analysis was employed to characterize the operating temperature of graphene-based devices using the experimentally determined currentvoltage data. The temperature of the hottest spot where the underlying SiO 2 layer was 300 nm thick was elevated up to about 70 °C at a 10 mW dissipated power. However, the operating temperature dropped to about 50 °C when the 300 nm thick SiO 2 layer was replaced with a 20 nm thick SiO 2 layer. Thermal management is very critical in the reliability of graphene-based high speed electronic devices because the high operating temperature can degrade the device performance.

KW - Channel temperature

KW - Graphene

KW - Transistor

UR - http://www.scopus.com/inward/record.url?scp=79955422286&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79955422286&partnerID=8YFLogxK

U2 - 10.1166/jnn.2010.2414

DO - 10.1166/jnn.2010.2414

M3 - Article

C2 - 21125824

AN - SCOPUS:79955422286

VL - 10

SP - 4889

EP - 4892

JO - Journal of Nanoscience and Nanotechnology

JF - Journal of Nanoscience and Nanotechnology

SN - 1533-4880

IS - 8

ER -