Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay

Young Ho Gong, Hyung Beom Jang, Sung Woo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and performance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the reduction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.

Original languageEnglish
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
Pages524-530
Number of pages7
DOIs
Publication statusPublished - 2013 Jul 5
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States
Duration: 2013 Mar 42013 Mar 6

Other

Other14th International Symposium on Quality Electronic Design, ISQED 2013
CountryUnited States
CitySanta Clara, CA
Period13/3/413/3/6

Fingerprint

Static random access storage
Wire
Microprocessor chips
Energy utilization

Keywords

  • access time
  • SRAM-eDRAM hybrid cache
  • wire delay

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Gong, Y. H., Jang, H. B., & Jung, S. W. (2013). Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 524-530). [6523661] https://doi.org/10.1109/ISQED.2013.6523661

Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay. / Gong, Young Ho; Jang, Hyung Beom; Jung, Sung Woo.

Proceedings - International Symposium on Quality Electronic Design, ISQED. 2013. p. 524-530 6523661.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gong, YH, Jang, HB & Jung, SW 2013, Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 6523661, pp. 524-530, 14th International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, United States, 13/3/4. https://doi.org/10.1109/ISQED.2013.6523661
Gong YH, Jang HB, Jung SW. Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2013. p. 524-530. 6523661 https://doi.org/10.1109/ISQED.2013.6523661
Gong, Young Ho ; Jang, Hyung Beom ; Jung, Sung Woo. / Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2013. pp. 524-530
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