Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure

Seung Geun Jung, Hyun-Yong Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10-4 A/um and contact resistivity of 3 × 10-9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.

Original languageEnglish
Title of host publicationEDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
Volume2017-January
ISBN (Electronic)9781538629079
DOIs
Publication statusPublished - 2017 Dec 1
Event13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Oct 182017 Oct 20

Other

Other13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017
CountryTaiwan, Province of China
CityHsinchu
Period17/10/1817/10/20

Fingerprint

Germanium
Field effect transistors
Metals
Semiconductor materials
Fermi level
Computer aided design
Doping (additives)

Keywords

  • 3-D TCAD simulation
  • CMOS
  • Germanium
  • Interlayer
  • Juntionless FET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Jung, S. G., & Yu, H-Y. (2017). Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure. In EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits (Vol. 2017-January, pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2017.8126520

Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure. / Jung, Seung Geun; Yu, Hyun-Yong.

EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jung, SG & Yu, H-Y 2017, Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure. in EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017, Hsinchu, Taiwan, Province of China, 17/10/18. https://doi.org/10.1109/EDSSC.2017.8126520
Jung SG, Yu H-Y. Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure. In EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-2 https://doi.org/10.1109/EDSSC.2017.8126520
Jung, Seung Geun ; Yu, Hyun-Yong. / Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure. EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-2
@inproceedings{bbd781cf42504b30829c8c0692b577cb,
title = "Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure",
abstract = "In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10-4 A/um and contact resistivity of 3 × 10-9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.",
keywords = "3-D TCAD simulation, CMOS, Germanium, Interlayer, Juntionless FET",
author = "Jung, {Seung Geun} and Hyun-Yong Yu",
year = "2017",
month = "12",
day = "1",
doi = "10.1109/EDSSC.2017.8126520",
language = "English",
volume = "2017-January",
pages = "1--2",
booktitle = "EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure

AU - Jung, Seung Geun

AU - Yu, Hyun-Yong

PY - 2017/12/1

Y1 - 2017/12/1

N2 - In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10-4 A/um and contact resistivity of 3 × 10-9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.

AB - In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10-4 A/um and contact resistivity of 3 × 10-9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.

KW - 3-D TCAD simulation

KW - CMOS

KW - Germanium

KW - Interlayer

KW - Juntionless FET

UR - http://www.scopus.com/inward/record.url?scp=85043520739&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85043520739&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2017.8126520

DO - 10.1109/EDSSC.2017.8126520

M3 - Conference contribution

AN - SCOPUS:85043520739

VL - 2017-January

SP - 1

EP - 2

BT - EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits

PB - Institute of Electrical and Electronics Engineers Inc.

ER -