Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure

Seung Geun Jung, Hyun-Yong Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10-4 A/um and contact resistivity of 3 × 10-9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.

Original languageEnglish
Title of host publicationEDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
Volume2017-January
ISBN (Electronic)9781538629079
DOIs
Publication statusPublished - 2017 Dec 1
Event13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Oct 182017 Oct 20

Other

Other13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017
CountryTaiwan, Province of China
CityHsinchu
Period17/10/1817/10/20

Keywords

  • 3-D TCAD simulation
  • CMOS
  • Germanium
  • Interlayer
  • Juntionless FET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Jung, S. G., & Yu, H-Y. (2017). Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure. In EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits (Vol. 2017-January, pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2017.8126520