Peripheral Circuit Optimization with Pre-charge Technique of Spin Transfer Torque MRAM Synapse Array

Minseok Kang, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Emerging device-based crossbar-array can improve energy efficiency and performance in Spiking Neural Network (SNN) that performs numerous addition and multiplication operations. However, for the large size of crossbar array, delay for SL voltage development increases due to large capacitances of bit-line, and area overhead of peripheral circuit increases significantly. In this paper, we propose STT-MRAM architecture for SNN by minimizing area overhead and operation delay with peripheral circuit optimization. When the proposed method is applied, in 512×512 crossbar array, voltage development delay is reduced by 5.75 (ns), making it possible to perform faster inference operation.

Original languageEnglish
Title of host publication2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665435536
DOIs
Publication statusPublished - 2021 Jun 27
Event36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021 - Jeju, Korea, Republic of
Duration: 2021 Jun 272021 Jun 30

Publication series

Name2021 36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021

Conference

Conference36th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2021
Country/TerritoryKorea, Republic of
CityJeju
Period21/6/2721/6/30

Keywords

  • STT-MRAM
  • Sourced line (SL) voltage developing delay
  • Spiking Neural Network (SNN)
  • pre-charge circuit

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems
  • Electrical and Electronic Engineering

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