Abstract
The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.
| Original language | English |
|---|---|
| Pages (from-to) | 245-252 |
| Number of pages | 8 |
| Journal | Microelectronics Journal |
| Volume | 33 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2002 Mar 1 |
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Keywords
- CMOS
- Dual phase frequency detectors
- Fast acquisition
- High frequency
- Low jitter
- Phase-locked loop
ASJC Scopus subject areas
- Control and Systems Engineering
- Electrical and Electronic Engineering
Cite this
Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition. / Woo, Youngshin; Jang, Young Min; Sung, Man Young.
In: Microelectronics Journal, Vol. 33, No. 3, 01.03.2002, p. 245-252.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition
AU - Woo, Youngshin
AU - Jang, Young Min
AU - Sung, Man Young
PY - 2002/3/1
Y1 - 2002/3/1
N2 - The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.
AB - The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.
KW - CMOS
KW - Dual phase frequency detectors
KW - Fast acquisition
KW - High frequency
KW - Low jitter
KW - Phase-locked loop
UR - http://www.scopus.com/inward/record.url?scp=0036498511&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036498511&partnerID=8YFLogxK
U2 - 10.1016/S0026-2692(01)00155-0
DO - 10.1016/S0026-2692(01)00155-0
M3 - Article
VL - 33
SP - 245
EP - 252
JO - Microelectronics Journal
JF - Microelectronics Journal
SN - 0959-8324
IS - 3
ER -