Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition

Youngshin Woo; Young Min Jang; Man Young Sung

doi:10.1016/S0026-2692(01)00155-0

Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition

Youngshin Woo, Young Min Jang, Man Young Sung

Honorary professors

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.

Original language	English
Pages (from-to)	245-252
Number of pages	8
Journal	Microelectronics Journal
Volume	33
Issue number	3
DOIs	https://doi.org/10.1016/S0026-2692(01)00155-0
Publication status	Published - 2002 Mar

Keywords

CMOS
Dual phase frequency detectors
Fast acquisition
High frequency
Low jitter
Phase-locked loop

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/S0026-2692(01)00155-0

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title = "Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition",

abstract = "The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.",

keywords = "CMOS, Dual phase frequency detectors, Fast acquisition, High frequency, Low jitter, Phase-locked loop",

author = "Youngshin Woo and Jang, {Young Min} and Sung, {Man Young}",

note = "Funding Information: This work was supported by grant No.1999-2-302-017-5 from the Basic Research Program of the Korea Science and Engineering Foundation.",

year = "2002",

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doi = "10.1016/S0026-2692(01)00155-0",

language = "English",

volume = "33",

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journal = "Microelectronics Journal",

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T1 - Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition

AU - Woo, Youngshin

AU - Jang, Young Min

AU - Sung, Man Young

N1 - Funding Information: This work was supported by grant No.1999-2-302-017-5 from the Basic Research Program of the Korea Science and Engineering Foundation.

PY - 2002/3

Y1 - 2002/3

N2 - The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.

AB - The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.

KW - CMOS

KW - Dual phase frequency detectors

KW - Fast acquisition

KW - High frequency

KW - Low jitter

KW - Phase-locked loop

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EP - 252

JO - Microelectronics Journal

JF - Microelectronics Journal

SN - 0959-8324

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ER -

Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition

Abstract

Keywords

ASJC Scopus subject areas

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