Abstract
The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior.
| Original language | English |
|---|---|
| Pages (from-to) | 245-252 |
| Number of pages | 8 |
| Journal | Microelectronics Journal |
| Volume | 33 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2002 Mar |
Keywords
- CMOS
- Dual phase frequency detectors
- Fast acquisition
- High frequency
- Low jitter
- Phase-locked loop
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering
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Woo, Y., Jang, Y. M., & Sung, M. Y. (2002). Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition. Microelectronics Journal, 33(3), 245-252. https://doi.org/10.1016/S0026-2692(01)00155-0