Phase-locked loops using digital calibration technique with counter

Chan Hui Jeong, Ammar Abdullah, Kwan Joo Lee, Hoon Ki Kim, Soo Won Kim

Research output: Contribution to journalArticlepeer-review


A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm2.

Original languageEnglish
Pages (from-to)320-324
Number of pages5
JournalTransactions of the Korean Institute of Electrical Engineers
Issue number2
Publication statusPublished - 2011 Feb


  • Charge pump phase-locked loop(CPPLL)
  • Charge pump(CP) mismatch
  • Digital calibration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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