Piecewise linear modulation technique for spread spectrum clock generation

Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two-and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that includes a high-resolution fractional divider to reduce quantization noise from a delta-sigma modulator. The SSCG with the two-slope-PWL modulation profile was fabricated in a 0.18 μ m 1P4M CMOS technology. The measured peak power reduction level of the two-slope-PWL modulation profile is 14.2 dB with 5000 ppm down spreading at 1.5 GHz. The SSCG occupies an active area of 0.49 mm 2 and consumes 40 mW of power at 1.5 GHz. The SSCG with the three-slope-PWL modulation profile was fabricated in a 0.13 μ m 1P6M CMOS technology. The measured peak power reduction level of the three-slope-PWL modulation profile is 10.3 and 10.52 dB with 5000 ppm down spreading at 162 and 270 MHz, respectively. The SSCG occupies an active area of 0.096 mm2 and dissipates 1 mW of power at 270 MHz.

Original languageEnglish
Article number6294463
Pages (from-to)1234-1245
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number7
DOIs
Publication statusPublished - 2013 Jan 1

    Fingerprint

Keywords

  • Electromagnetic interference (EMI) reduction
  • phase-locked loop (PLL)
  • piecewise linear approximation
  • spread spectrum clock generation (SSCG)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this