Pipelined CPU design with FPGA in teaching computer architecture

Jong Hyuk Lee, Seung Eun Lee, Heon Chang Yu, Taeweon Suh

Research output: Contribution to journalArticlepeer-review

29 Citations (Scopus)


This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in that the devised project requires the implementation of a real CPU instead of utilizing simulators or just experimenting with ready-made complete CPU models.

Original languageEnglish
Article number6093707
Pages (from-to)341-348
Number of pages8
JournalIEEE Transactions on Education
Issue number3
Publication statusPublished - 2012


  • Computer architecture
  • education
  • field programmable gate array (FPGA)
  • hands-on learning
  • incremental learning
  • pipeline
  • problem-based learning (PBL)

ASJC Scopus subject areas

  • Education
  • Electrical and Electronic Engineering


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