Pipelined VLSI architecture of the Viterbi decoder for IMT-2000

Byonghyo Shim, Jung Chul Suh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

An improved VLSI architecture for the high-speed Viterbi decoder is proposed. We partitioned the datapath of the Viterbi decoder into largely 3 pipeline stages and to reduce the operation overhead of the ACSU, removed the minimum metric selection logic and exploited constant subtraction scheme for the metric rescaling. This can be done by using unsigned arithmetic and the overflow detection unit. We also discuss unnecessity of minimum metric selection logic in the point of truncation effects. Simulation results demonstrate that if the traceback depth is set long enough, the arbitrary state decoding can be used without much disadvantage over the best state decoding. The SMU pipelining architecture based on the modified traceback algorithm is also presented. By exploiting the 2 registers and multiplexor, we made one-stage pipeline cell and by cascading them, the traceback operation without LIFO or some complex memory controller can be achieved with a latency of only 2T.

Original languageEnglish
Title of host publicationConference Record / IEEE Global Telecommunications Conference
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Volume1
Publication statusPublished - 1999 Dec 1
Externally publishedYes
Event1999 IEEE Global Telecommunication Conference - GLOBECOM'99 - Rio de Janeiro, Braz
Duration: 1999 Dec 51999 Dec 9

Other

Other1999 IEEE Global Telecommunication Conference - GLOBECOM'99
CityRio de Janeiro, Braz
Period99/12/599/12/9

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Global and Planetary Change

Cite this

Shim, B., & Suh, J. C. (1999). Pipelined VLSI architecture of the Viterbi decoder for IMT-2000. In Conference Record / IEEE Global Telecommunications Conference (Vol. 1). Piscataway, NJ, United States: IEEE.