Poly-Si thin film transistors with a source overlap and a drain offset: leakage current characteristics

The electrical characteristics of hydrogen passivated polycrystalline-silicon p-channel metal-oxide-semiconductor thin-film transistors (poly-Si PMOS TFTs) for high density memory devices have been investigated. A lightly doped offset (LDO) structure was adopted to reduce the electric field induced in the drain region. Compared with the on-current, the off-current was reduced significantly with an LDO length. As a result, the TFT with an LDO presented the enhanced on/off current ratio. However, it still has a drawback of reducing the on-current due to increased parasitic resistance. To reduce this effect, a source overlap structure was introduced. Although the on current was slightly improved at a longer source overlap length due to channel length reduction, the dependence of the on/off current ratio on a source overlap length was small compared with that on an LDO length. In the measurement of leakage currents, the lower channel and gate breakdown voltages were obtained at the longer source overlap structure.