PP-cache: A partitioned power-aware instruction cache architecture

Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a new instruction cache architecture, named Partitioned Power-aware instruction cache (PP-cache), for reducing dynamic energy consumption in the instruction cache by partitioning it to small sub-caches. When a request comes into the PP-cache, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not activated. The PP-cache reduces dynamic energy consumption by reducing the activated cache size and eliminating the energy consumed in tag matching. Simulation results show that the PP-cache reduces dynamic energy consumption by 34-56%. This paper also proposes the technique to reduce leakage energy consumption in the PP-cache, which turns off the lines that do not have valid data dynamically. Simulation results show that the proposed technique reduces leakage energy consumption in the PP-cache by 74-85%.

Original languageEnglish
Pages (from-to)268-279
Number of pages12
JournalMicroprocessors and Microsystems
Volume30
Issue number5
DOIs
Publication statusPublished - 2006 Aug 1

Keywords

  • Dynamic energy
  • Instruction cache
  • Leakage energy
  • Low-power design
  • Partitioned cache

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

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