Practical approach to power integrity-driven design process for power-delivery networks

Baekseok Ko, Joowon Kim, Jaemin Ryoo, Chulsoon Hwang, Chan Keun Kwon, Soo-Won Kim

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.

Original languageEnglish
Pages (from-to)448-455
Number of pages8
JournalIET Circuits, Devices and Systems
Volume10
Issue number5
DOIs
Publication statusPublished - 2016 Sep 1

Fingerprint

Program processors
Ceramic capacitors
Ball grid arrays
Electric potential
Multilayers
Networks (circuits)
System-on-chip

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Practical approach to power integrity-driven design process for power-delivery networks. / Ko, Baekseok; Kim, Joowon; Ryoo, Jaemin; Hwang, Chulsoon; Kwon, Chan Keun; Kim, Soo-Won.

In: IET Circuits, Devices and Systems, Vol. 10, No. 5, 01.09.2016, p. 448-455.

Research output: Contribution to journalArticle

Ko, Baekseok ; Kim, Joowon ; Ryoo, Jaemin ; Hwang, Chulsoon ; Kwon, Chan Keun ; Kim, Soo-Won. / Practical approach to power integrity-driven design process for power-delivery networks. In: IET Circuits, Devices and Systems. 2016 ; Vol. 10, No. 5. pp. 448-455.
@article{973b8abde2334385976f7b493e699f5c,
title = "Practical approach to power integrity-driven design process for power-delivery networks",
abstract = "The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6{\%}, while the difference in voltage noise ripple was 2.69{\%} for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.",
author = "Baekseok Ko and Joowon Kim and Jaemin Ryoo and Chulsoon Hwang and Kwon, {Chan Keun} and Soo-Won Kim",
year = "2016",
month = "9",
day = "1",
doi = "10.1049/iet-cds.2015.0285",
language = "English",
volume = "10",
pages = "448--455",
journal = "IET Circuits, Devices and Systems",
issn = "1751-858X",
publisher = "Institution of Engineering and Technology",
number = "5",

}

TY - JOUR

T1 - Practical approach to power integrity-driven design process for power-delivery networks

AU - Ko, Baekseok

AU - Kim, Joowon

AU - Ryoo, Jaemin

AU - Hwang, Chulsoon

AU - Kwon, Chan Keun

AU - Kim, Soo-Won

PY - 2016/9/1

Y1 - 2016/9/1

N2 - The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.

AB - The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.

UR - http://www.scopus.com/inward/record.url?scp=84988446651&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84988446651&partnerID=8YFLogxK

U2 - 10.1049/iet-cds.2015.0285

DO - 10.1049/iet-cds.2015.0285

M3 - Article

AN - SCOPUS:84988446651

VL - 10

SP - 448

EP - 455

JO - IET Circuits, Devices and Systems

JF - IET Circuits, Devices and Systems

SN - 1751-858X

IS - 5

ER -