TY - JOUR
T1 - Practical silicon-backside-protection method for abnormally detection
AU - Yi, Kyungsuk
AU - Park, Minsu
AU - Cha, Sungyong
AU - Kim, Seungjoo
N1 - Funding Information:
This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP)(IITP-2017-0-00184, Self-Learning Cyber Immune Technology Development)
Funding Information:
This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP)(IITP-2017-0-00184, Self-Learning Cyber Immune Technology Development).
Publisher Copyright:
© 2019, Institute of Electronics Engineers of Korea. All rights reserved.
PY - 2019/12
Y1 - 2019/12
N2 - Nowadays, security ICs such as cryptographic modules, TPMs (Trust Platform Modules), connected car ICs, and smart card protection methods have been enhanced due to the introduction of a variety of new attack methods. Additionally, their protection mechanisms are continuously being developed and evaluated. For these reasons, attacking or hacking security chips is now more difficult than it ever has been. Nevertheless, IC failure analysis tools are being greatly improved, with many developers using them. Additionally, in using these tools, many cases involve analyzing the integrated circuit. By exploiting this analysis, attackers can perform invasive attacks [1] or hack the IC from the backside more easily than ever before. However, due to the structure of an IC, making a circuit on the back side of the silicon is more difficult than doing so on the front side. In order to resolve this issue, this paper proposes a practical silicon-backside-protection method that can protect the IC from backside attacks while minimizing its size and increasing its coverage. The proposed method uses capacitance located between the metal-layer which is unused for routing, and uses it for a passive shield (dummy shield) area.
AB - Nowadays, security ICs such as cryptographic modules, TPMs (Trust Platform Modules), connected car ICs, and smart card protection methods have been enhanced due to the introduction of a variety of new attack methods. Additionally, their protection mechanisms are continuously being developed and evaluated. For these reasons, attacking or hacking security chips is now more difficult than it ever has been. Nevertheless, IC failure analysis tools are being greatly improved, with many developers using them. Additionally, in using these tools, many cases involve analyzing the integrated circuit. By exploiting this analysis, attackers can perform invasive attacks [1] or hack the IC from the backside more easily than ever before. However, due to the structure of an IC, making a circuit on the back side of the silicon is more difficult than doing so on the front side. In order to resolve this issue, this paper proposes a practical silicon-backside-protection method that can protect the IC from backside attacks while minimizing its size and increasing its coverage. The proposed method uses capacitance located between the metal-layer which is unused for routing, and uses it for a passive shield (dummy shield) area.
KW - Abnormally detection
KW - Active shield
KW - Connected car
KW - Integrated circuit attack
KW - Passive shield
KW - Secure design
KW - Secure shield
KW - Silicon-backside protection
UR - http://www.scopus.com/inward/record.url?scp=85077280618&partnerID=8YFLogxK
U2 - 10.5573/JSTS.2019.19.6.577
DO - 10.5573/JSTS.2019.19.6.577
M3 - Article
AN - SCOPUS:85077280618
SN - 1598-1657
VL - 19
SP - 577
EP - 584
JO - Journal of Semiconductor Technology and Science
JF - Journal of Semiconductor Technology and Science
IS - 6
ER -