Practice and experience of an embedded processor core modeling

Gi Ho Park, Sung Woo Jung, Han Jong Kim, Jung Bin Im, Jung Wook Park, Shin Dug Kim, Sung Bae Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Pages621-630
Number of pages10
Volume4208 LNCS
Publication statusPublished - 2006 Oct 31
Event2nd International Conference on High Performance Computing and Communications, HPCC 2006 - Munich, Germany
Duration: 2006 Sep 132006 Sep 15

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4208 LNCS
ISSN (Print)03029743
ISSN (Electronic)16113349

Other

Other2nd International Conference on High Performance Computing and Communications, HPCC 2006
CountryGermany
CityMunich
Period06/9/1306/9/15

Fingerprint

Environment Design
Benchmarking
Embedded Processor
Software
Modeling
Simulator
Simulators
Application programs
Model
Simulation Environment
Experience
Benchmark
Iteration
Cycle
Design
Simulation

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

Cite this

Park, G. H., Jung, S. W., Kim, H. J., Im, J. B., Park, J. W., Kim, S. D., & Park, S. B. (2006). Practice and experience of an embedded processor core modeling. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4208 LNCS, pp. 621-630). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4208 LNCS).

Practice and experience of an embedded processor core modeling. / Park, Gi Ho; Jung, Sung Woo; Kim, Han Jong; Im, Jung Bin; Park, Jung Wook; Kim, Shin Dug; Park, Sung Bae.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4208 LNCS 2006. p. 621-630 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4208 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Park, GH, Jung, SW, Kim, HJ, Im, JB, Park, JW, Kim, SD & Park, SB 2006, Practice and experience of an embedded processor core modeling. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). vol. 4208 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4208 LNCS, pp. 621-630, 2nd International Conference on High Performance Computing and Communications, HPCC 2006, Munich, Germany, 06/9/13.
Park GH, Jung SW, Kim HJ, Im JB, Park JW, Kim SD et al. Practice and experience of an embedded processor core modeling. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4208 LNCS. 2006. p. 621-630. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
Park, Gi Ho ; Jung, Sung Woo ; Kim, Han Jong ; Im, Jung Bin ; Park, Jung Wook ; Kim, Shin Dug ; Park, Sung Bae. / Practice and experience of an embedded processor core modeling. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4208 LNCS 2006. pp. 621-630 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
@inproceedings{727182641dbe42259887ed6d63f05506,
title = "Practice and experience of an embedded processor core modeling",
abstract = "This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97{\%} compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).",
author = "Park, {Gi Ho} and Jung, {Sung Woo} and Kim, {Han Jong} and Im, {Jung Bin} and Park, {Jung Wook} and Kim, {Shin Dug} and Park, {Sung Bae}",
year = "2006",
month = "10",
day = "31",
language = "English",
isbn = "3540393684",
volume = "4208 LNCS",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
pages = "621--630",
booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

}

TY - GEN

T1 - Practice and experience of an embedded processor core modeling

AU - Park, Gi Ho

AU - Jung, Sung Woo

AU - Kim, Han Jong

AU - Im, Jung Bin

AU - Park, Jung Wook

AU - Kim, Shin Dug

AU - Park, Sung Bae

PY - 2006/10/31

Y1 - 2006/10/31

N2 - This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).

AB - This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).

UR - http://www.scopus.com/inward/record.url?scp=33750305325&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33750305325&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33750305325

SN - 3540393684

SN - 9783540393689

VL - 4208 LNCS

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 621

EP - 630

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

ER -