Abstract
With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.
| Original language | English |
|---|---|
| Pages (from-to) | 123-136 |
| Number of pages | 14 |
| Journal | Journal of Signal Processing Systems |
| Volume | 73 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2013 Nov 1 |
Fingerprint
Keywords
- Embedded SRAM
- Error control code
- H.264
- Low voltage operation
- Multimedia
ASJC Scopus subject areas
- Hardware and Architecture
- Information Systems
- Signal Processing
- Theoretical Computer Science
- Control and Systems Engineering
- Modelling and Simulation
Cite this
Priority based error correction code (ECC) for the embedded SRAM memories in H.264 system. / Lee, Insoo; Kwon, Jinmo; Park, Jongsun.
In: Journal of Signal Processing Systems, Vol. 73, No. 2, 01.11.2013, p. 123-136.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Priority based error correction code (ECC) for the embedded SRAM memories in H.264 system
AU - Lee, Insoo
AU - Kwon, Jinmo
AU - Park, Jongsun
PY - 2013/11/1
Y1 - 2013/11/1
N2 - With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.
AB - With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.
KW - Embedded SRAM
KW - Error control code
KW - H.264
KW - Low voltage operation
KW - Multimedia
UR - http://www.scopus.com/inward/record.url?scp=84881481080&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881481080&partnerID=8YFLogxK
U2 - 10.1007/s11265-013-0736-4
DO - 10.1007/s11265-013-0736-4
M3 - Article
AN - SCOPUS:84881481080
VL - 73
SP - 123
EP - 136
JO - Journal of Signal Processing Systems
JF - Journal of Signal Processing Systems
SN - 1939-8018
IS - 2
ER -