Process algebraic model of superscalar processor programs for instruction level timing analysis

Hee J. Yoo, Jin Young Choi

Research output: Contribution to journalArticle

Abstract

This paper illustrates a formal technique for describing timing properties and resource constraints of pipelined out of order superscalar processor instructions at a high level. The degree of parallelism depends on the multiplicity of hardware functional units as well as data dependencies among instructions. Thus, the timing properties of a superscalar program are difficult to analyze and predict. We describe how to model the instruction level architecture of a superscalar processor using ACSR and how to derive the temporal behavior of an assembly program using ACSR laws. Our approach is to model superscalar processor registers as ACSR resources, instructions as ACSR processes, and use ACSR priorities to achieve maximum possible instruction-level parallelism.

Original languageEnglish
Pages (from-to)180-184
Number of pages5
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2763
Publication statusPublished - 2003 Dec 1

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Superscalar Processor
Timing Analysis
Program processors
Program assemblers
Timing
Superscalar
Instruction Level Parallelism
Data Dependency
Resource Constraints
Hardware
Parallelism
Multiplicity
Model
Predict
Resources
Unit

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Computer Science(all)
  • Theoretical Computer Science

Cite this

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