This paper illustrates a formal technique for describing timing properties and resource constraints of pipelined out of order superscalar processor instructions at a high level. The degree of parallelism depends on the multiplicity of hardware functional units as well as data dependencies among instructions. Thus, the timing properties of a superscalar program are difficult to analyze and predict. We describe how to model the instruction level architecture of a superscalar processor using ACSR and how to derive the temporal behavior of an assembly program using ACSR laws. Our approach is to model superscalar processor registers as ACSR resources, instructions as ACSR processes, and use ACSR priorities to achieve maximum possible instruction-level parallelism.