Process variation-tolerant 3D microprocessor design: An efficient architectural solution

Joonho Kong, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Process variation is one of the most challenging problems for 3D microprocessors. This is because stacked dies are likely to have fairly different characteristics due to wafer-to-wafer (W2W) variations, which may severely hurt yield of 3D microprocessors. In this paper, we introduce a process variation-tolerant 3D microprocessor design that exploits an architectural insight: narrow-width values. The main target of our technique is last-level caches (LLCs), which are composed of several dies. By storing only the meaningful bit parts within a data word into the LLCs while discarding the zero bit parts (which can be recovered by the zero-extension logic), our proposed technique improves a storage efficiency of the LLCs, which eventually enhances cache yield. According to our evaluation results, our technique significantly improves cache yield in a performance-/energy-efficient manner.

Original languageEnglish
Title of host publicationICICDT 2013 - International Conference on IC Design and Technology, Proceedings
Pages45-48
Number of pages4
DOIs
Publication statusPublished - 2013
Event2013 International Conference on IC Design and Technology, ICICDT 2013 - Pavia, Italy
Duration: 2013 May 292013 May 31

Publication series

NameICICDT 2013 - International Conference on IC Design and Technology, Proceedings

Other

Other2013 International Conference on IC Design and Technology, ICICDT 2013
CountryItaly
CityPavia
Period13/5/2913/5/31

Keywords

  • 3D microprocessor
  • last-level cache
  • narrowwidth value
  • process variation
  • yield

ASJC Scopus subject areas

  • Hardware and Architecture

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