Processor-based decoupled PDP timing controller design

Yeoul Na, Seok Joong Hwang, Cheol Ho Lee, Junkyu Min, Taejin Kim, Seon Wook Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Conference on Consumer Electronics
Pages867-868
Number of pages2
DOIs
Publication statusPublished - 2011 Mar 28
Event2011 IEEE International Conference on Consumer Electronics, ICCE 2011 - Las Vegas, NV, United States
Duration: 2011 Jan 92011 Jan 12

Other

Other2011 IEEE International Conference on Consumer Electronics, ICCE 2011
CountryUnited States
CityLas Vegas, NV
Period11/1/911/1/12

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

Cite this

Na, Y., Hwang, S. J., Lee, C. H., Min, J., Kim, T., & Kim, S. W. (2011). Processor-based decoupled PDP timing controller design. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics (pp. 867-868). [5722909] https://doi.org/10.1109/ICCE.2011.5722909