Prominoc: An efficient network-on-chip design for flexible data permutation

Phi Hung Pham, Jongsun Park, Chulwoo Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18μm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of 0.473mm2 (52kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.

Original languageEnglish
Pages (from-to)861-866
Number of pages6
JournalIEICE Electronics Express
Volume7
Issue number12
DOIs
Publication statusPublished - 2010 Jun 25

Fingerprint

permutations
chips
switching circuits
Switching circuits
CMOS
bandwidth
cells
Bandwidth
Network-on-chip

Keywords

  • Data permutation
  • Network-on-chip
  • On-chip router

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Prominoc : An efficient network-on-chip design for flexible data permutation. / Pham, Phi Hung; Park, Jongsun; Kim, Chulwoo.

In: IEICE Electronics Express, Vol. 7, No. 12, 25.06.2010, p. 861-866.

Research output: Contribution to journalArticle

@article{0bdee70c3b584f5fb50b64a753db2683,
title = "Prominoc: An efficient network-on-chip design for flexible data permutation",
abstract = "This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18μm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of 0.473mm2 (52kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.",
keywords = "Data permutation, Network-on-chip, On-chip router",
author = "Pham, {Phi Hung} and Jongsun Park and Chulwoo Kim",
year = "2010",
month = "6",
day = "25",
doi = "10.1587/elex.7.861",
language = "English",
volume = "7",
pages = "861--866",
journal = "IEICE Electronics Express",
issn = "1349-2543",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "12",

}

TY - JOUR

T1 - Prominoc

T2 - An efficient network-on-chip design for flexible data permutation

AU - Pham, Phi Hung

AU - Park, Jongsun

AU - Kim, Chulwoo

PY - 2010/6/25

Y1 - 2010/6/25

N2 - This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18μm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of 0.473mm2 (52kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.

AB - This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18μm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of 0.473mm2 (52kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.

KW - Data permutation

KW - Network-on-chip

KW - On-chip router

UR - http://www.scopus.com/inward/record.url?scp=77954246828&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77954246828&partnerID=8YFLogxK

U2 - 10.1587/elex.7.861

DO - 10.1587/elex.7.861

M3 - Article

AN - SCOPUS:77954246828

VL - 7

SP - 861

EP - 866

JO - IEICE Electronics Express

JF - IEICE Electronics Express

SN - 1349-2543

IS - 12

ER -