This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18μm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4Gb/s, while occupying a compact area of 0.473mm2 (52kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.
- Data permutation
- On-chip router
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering