PVT variation tolerant current source with on-chip digital self-calibration

Moo Young Kim, Hokyu Lee, Chulwoo Kim

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.

Original languageEnglish
Article number5720543
Pages (from-to)737-741
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number4
DOIs
Publication statusPublished - 2012 Apr

Keywords

  • All digital gates
  • current source
  • on-chip
  • process, supply voltage, and temperature (PVT) detector
  • self-calibration

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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