PVT variation tolerant current source with on-chip digital self-calibration

Moo Young Kim, Hokyu Lee, Chulwoo Kim

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.

Original languageEnglish
Article number5720543
Pages (from-to)737-741
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number4
DOIs
Publication statusPublished - 2012 Apr 1

Fingerprint

Calibration
Electric potential
Temperature
Electric power utilization
Detectors
Bandwidth

Keywords

  • All digital gates
  • current source
  • on-chip
  • process, supply voltage, and temperature (PVT) detector
  • self-calibration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

PVT variation tolerant current source with on-chip digital self-calibration. / Kim, Moo Young; Lee, Hokyu; Kim, Chulwoo.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, 5720543, 01.04.2012, p. 737-741.

Research output: Contribution to journalArticle

@article{29569005c3c74da2aa8d9b5e755d01a4,
title = "PVT variation tolerant current source with on-chip digital self-calibration",
abstract = "A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2{\%} is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.",
keywords = "All digital gates, current source, on-chip, process, supply voltage, and temperature (PVT) detector, self-calibration",
author = "Kim, {Moo Young} and Hokyu Lee and Chulwoo Kim",
year = "2012",
month = "4",
day = "1",
doi = "10.1109/TVLSI.2011.2109971",
language = "English",
volume = "20",
pages = "737--741",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - PVT variation tolerant current source with on-chip digital self-calibration

AU - Kim, Moo Young

AU - Lee, Hokyu

AU - Kim, Chulwoo

PY - 2012/4/1

Y1 - 2012/4/1

N2 - A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.

AB - A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μ W at a supply voltage of 1.0 V.

KW - All digital gates

KW - current source

KW - on-chip

KW - process, supply voltage, and temperature (PVT) detector

KW - self-calibration

UR - http://www.scopus.com/inward/record.url?scp=84858997296&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84858997296&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2011.2109971

DO - 10.1109/TVLSI.2011.2109971

M3 - Article

VL - 20

SP - 737

EP - 741

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

M1 - 5720543

ER -