RAPTOR: A single chip multiprocessor

Sang Won Lee, Yun Seob Song, Soo Won Kim, Hyeong Cheol Oh, Woo Jang Hahn

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages217-220
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
Publication statusPublished - 1999
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 1999 Aug 231999 Aug 25

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
CountryKorea, Republic of
CitySeoul
Period99/8/2399/8/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Lee, S. W., Song, Y. S., Kim, S. W., Oh, H. C., & Hahn, W. J. (1999). RAPTOR: A single chip multiprocessor. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 217-220). [824067] (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824067