RAPTOR: A single chip multiprocessor

Sang Won Lee; Yun Seob Song; Soo Won Kim; Hyeong Cheol Oh; Woo Jang Hahn

doi:10.1109/APASIC.1999.824067

RAPTOR: A single chip multiprocessor

Sang Won Lee, Yun Seob Song, Soo Won Kim, Hyeong Cheol Oh, Woo Jang Hahn

* Honorary professors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	217-220
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824067
Publication status	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 1999 Aug 23 → 1999 Aug 25

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	99/8/23 → 99/8/25

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/APASIC.1999.824067

Cite this

RAPTOR : A single chip multiprocessor. / Lee, Sang Won; Song, Yun Seob; Kim, Soo Won et al.

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 217-220 824067 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, SW, Song, YS, Kim, SW, Oh, HC & Hahn, WJ 1999, RAPTOR: A single chip multiprocessor. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824067, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 217-220, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 99/8/23. https://doi.org/10.1109/APASIC.1999.824067

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AB - A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines.

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BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 23 August 1999 through 25 August 1999

ER -

RAPTOR: A single chip multiprocessor

Abstract

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ASJC Scopus subject areas

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