Reconfigurable ECC for adaptive protection of memory

Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundancy) remain effective in healing manufacturing defects and process variation induced failures in nanoscale memory. They are, however, not effective in improving robustness under various run-time failures. Increasing run-time failures in memory, specifically in case of low-voltage low-power memory, has emerged as a major design challenge. Traditionally, a uniform worst-case protection using Error Correction Code (ECC) is used for all blocks in a large memory array for runt-time error resiliency. However, with both spatial and temporal shift in intrinsic reliability of a memory block, such uniform protection can be unattractive in terms of either ECC overhead or protection level. We propose a novel Reconfigurable ECC approach, which can adapt, in space and time, to varying reliability of memory blocks by using an ECC that can provide the right amount of protection for a memory block at a given time. We show that such an approach is extremely effective in diverse applications.

Original languageEnglish
Title of host publication2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
Pages1085-1088
Number of pages4
DOIs
Publication statusPublished - 2013
Event2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH, United States
Duration: 2013 Aug 42013 Aug 7

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
CountryUnited States
CityColumbus, OH
Period13/8/413/8/7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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