Reduction of Threshold Voltage Hysteresis of MoS₂ Transistors with 3-Aminopropyltriethoxysilane Passivation and Its Application for Improved Synaptic Behavior

Although molybdenum disulfide (MoS₂) is highlighted as a promising channel material, MoS₂-based field-effect transistors (FETs) have a large threshold voltage hysteresis (ΔV_TH) from interface traps at their gate interfaces. In this work, the ΔV_TH of MoS₂ FETs is significantly reduced by inserting a 3-aminopropyltriethoxysilane (APTES) passivation layer at the MoS₂/SiO₂ gate interface owing to passivation of the interface traps. The ΔV_TH is reduced from 23 to 10.8 V by inserting the 1%-APTES passivation layers because APTES passivation prevents trapping and detrapping of electrons, which are the major source of the ΔV_TH. The reduction in the density of interface traps (D_it) is confirmed by the improvement of the subthreshold swing (SS) after inserting the APTES layer. Furthermore, the improvement in the synaptic characteristics of the MoS₂ FET through the APTES passivation is investigated. Both inhibitory and excitatory postsynaptic currents (PSC) are increased by 33% owing to the reduction in the ΔV_TH and the n-type doping effect of the APTES layer; moreover, the linearity of PSC characteristics is significantly improved because the reduction in ΔV_TH enables the synaptic operation to be over the threshold region, which is linear. The application of the APTES gate passivation technique to MoS₂ FETs is promising for reliable and accurate synaptic applications in neuromorphic computing technology as well as for the next-generation complementary logic applications.