Abstract
Although molybdenum disulfide (MoS2) is highlighted as a promising channel material, MoS2-based field-effect transistors (FETs) have a large threshold voltage hysteresis (ΔVTH) from interface traps at their gate interfaces. In this work, the ΔVTH of MoS2 FETs is significantly reduced by inserting a 3-aminopropyltriethoxysilane (APTES) passivation layer at the MoS2/SiO2 gate interface owing to passivation of the interface traps. The ΔVTH is reduced from 23 to 10.8 V by inserting the 1%-APTES passivation layers because APTES passivation prevents trapping and detrapping of electrons, which are the major source of the ΔVTH. The reduction in the density of interface traps (Dit) is confirmed by the improvement of the subthreshold swing (SS) after inserting the APTES layer. Furthermore, the improvement in the synaptic characteristics of the MoS2 FET through the APTES passivation is investigated. Both inhibitory and excitatory postsynaptic currents (PSC) are increased by 33% owing to the reduction in the ΔVTH and the n-type doping effect of the APTES layer; moreover, the linearity of PSC characteristics is significantly improved because the reduction in ΔVTH enables the synaptic operation to be over the threshold region, which is linear. The application of the APTES gate passivation technique to MoS2 FETs is promising for reliable and accurate synaptic applications in neuromorphic computing technology as well as for the next-generation complementary logic applications.
| Original language | English |
|---|---|
| Pages (from-to) | 20949-20955 |
| Number of pages | 7 |
| Journal | ACS Applied Materials and Interfaces |
| Volume | 11 |
| Issue number | 23 |
| DOIs | |
| Publication status | Published - 2019 Jun 12 |
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Keywords
- 3-aminopropyltriethoxysilane
- molybdenum disulfide
- surface passivation
- synapse applications
- threshold voltage hysteresis
ASJC Scopus subject areas
- Materials Science(all)
Cite this
Reduction of Threshold Voltage Hysteresis of MoS2 Transistors with 3-Aminopropyltriethoxysilane Passivation and Its Application for Improved Synaptic Behavior. / Han, Kyu Hyun; Kim, Gwang Sik; Park, June; Kim, Seung Geun; Park, Jin Hong; Yu, Hyun-Yong.
In: ACS Applied Materials and Interfaces, Vol. 11, No. 23, 12.06.2019, p. 20949-20955.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Reduction of Threshold Voltage Hysteresis of MoS2 Transistors with 3-Aminopropyltriethoxysilane Passivation and Its Application for Improved Synaptic Behavior
AU - Han, Kyu Hyun
AU - Kim, Gwang Sik
AU - Park, June
AU - Kim, Seung Geun
AU - Park, Jin Hong
AU - Yu, Hyun-Yong
PY - 2019/6/12
Y1 - 2019/6/12
N2 - Although molybdenum disulfide (MoS2) is highlighted as a promising channel material, MoS2-based field-effect transistors (FETs) have a large threshold voltage hysteresis (ΔVTH) from interface traps at their gate interfaces. In this work, the ΔVTH of MoS2 FETs is significantly reduced by inserting a 3-aminopropyltriethoxysilane (APTES) passivation layer at the MoS2/SiO2 gate interface owing to passivation of the interface traps. The ΔVTH is reduced from 23 to 10.8 V by inserting the 1%-APTES passivation layers because APTES passivation prevents trapping and detrapping of electrons, which are the major source of the ΔVTH. The reduction in the density of interface traps (Dit) is confirmed by the improvement of the subthreshold swing (SS) after inserting the APTES layer. Furthermore, the improvement in the synaptic characteristics of the MoS2 FET through the APTES passivation is investigated. Both inhibitory and excitatory postsynaptic currents (PSC) are increased by 33% owing to the reduction in the ΔVTH and the n-type doping effect of the APTES layer; moreover, the linearity of PSC characteristics is significantly improved because the reduction in ΔVTH enables the synaptic operation to be over the threshold region, which is linear. The application of the APTES gate passivation technique to MoS2 FETs is promising for reliable and accurate synaptic applications in neuromorphic computing technology as well as for the next-generation complementary logic applications.
AB - Although molybdenum disulfide (MoS2) is highlighted as a promising channel material, MoS2-based field-effect transistors (FETs) have a large threshold voltage hysteresis (ΔVTH) from interface traps at their gate interfaces. In this work, the ΔVTH of MoS2 FETs is significantly reduced by inserting a 3-aminopropyltriethoxysilane (APTES) passivation layer at the MoS2/SiO2 gate interface owing to passivation of the interface traps. The ΔVTH is reduced from 23 to 10.8 V by inserting the 1%-APTES passivation layers because APTES passivation prevents trapping and detrapping of electrons, which are the major source of the ΔVTH. The reduction in the density of interface traps (Dit) is confirmed by the improvement of the subthreshold swing (SS) after inserting the APTES layer. Furthermore, the improvement in the synaptic characteristics of the MoS2 FET through the APTES passivation is investigated. Both inhibitory and excitatory postsynaptic currents (PSC) are increased by 33% owing to the reduction in the ΔVTH and the n-type doping effect of the APTES layer; moreover, the linearity of PSC characteristics is significantly improved because the reduction in ΔVTH enables the synaptic operation to be over the threshold region, which is linear. The application of the APTES gate passivation technique to MoS2 FETs is promising for reliable and accurate synaptic applications in neuromorphic computing technology as well as for the next-generation complementary logic applications.
KW - 3-aminopropyltriethoxysilane
KW - molybdenum disulfide
KW - surface passivation
KW - synapse applications
KW - threshold voltage hysteresis
UR - http://www.scopus.com/inward/record.url?scp=85066974240&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85066974240&partnerID=8YFLogxK
U2 - 10.1021/acsami.9b01391
DO - 10.1021/acsami.9b01391
M3 - Article
C2 - 31117422
AN - SCOPUS:85066974240
VL - 11
SP - 20949
EP - 20955
JO - ACS applied materials & interfaces
JF - ACS applied materials & interfaces
SN - 1944-8244
IS - 23
ER -