Reliable cache memory design for sensor networks

Hyung Beom Jang, Ali Kashif, Myong Soon Park, Sung Woo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

With the advance of processor technology, critical device parameters are significantly affected by the process variation. Subsequently, these critical parameters result in high access latencies, significant leakage power and abnormal high temperature. Cache memory circuits are easily affected by the process variation than any other hardware components; due to the densely tied transistors. Moreover, the process variation decreases both the yield of the chip and the lifetime of cache memory used in resource limited devices. Cache memory used in resource limited devices may get affected easily by the process variation due to hostile environments. In this paper, we introduce a simple but very effective process variation tolerant technique using the conventional cache replacement policies. This technique selects the cache block replacement victims excluding the affected cache block by the process variation. Without additional hardware components, the proposed technique can handle the affected cache block minimizing the performance loss. Our experiments show that when we adopted our proposed idea, the performance penalty is less than 1 % in case of 12.5% cache blocks cannot be used. Under the severe process variation, our proposed idea deteriorates the performance by only about 2%. By applying our technique in cache memory of resource limited devices, sensor nodes used in sensor networks will be more reliable.

Original languageEnglish
Title of host publicationProceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
Pages651-656
Number of pages6
Volume1
DOIs
Publication statusPublished - 2008 Dec 29
Event3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008 - Busan, Korea, Republic of
Duration: 2008 Nov 112008 Nov 13

Other

Other3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
CountryKorea, Republic of
CityBusan
Period08/11/1108/11/13

Fingerprint

Cache memory
Sensor networks
Hardware
Sensor nodes
Transistors
Networks (circuits)
Experiments
Temperature

ASJC Scopus subject areas

  • Information Systems
  • Software

Cite this

Jang, H. B., Kashif, A., Park, M. S., & Jung, S. W. (2008). Reliable cache memory design for sensor networks. In Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008 (Vol. 1, pp. 651-656). [4682100] https://doi.org/10.1109/ICCIT.2008.125

Reliable cache memory design for sensor networks. / Jang, Hyung Beom; Kashif, Ali; Park, Myong Soon; Jung, Sung Woo.

Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008. Vol. 1 2008. p. 651-656 4682100.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jang, HB, Kashif, A, Park, MS & Jung, SW 2008, Reliable cache memory design for sensor networks. in Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008. vol. 1, 4682100, pp. 651-656, 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008, Busan, Korea, Republic of, 08/11/11. https://doi.org/10.1109/ICCIT.2008.125
Jang HB, Kashif A, Park MS, Jung SW. Reliable cache memory design for sensor networks. In Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008. Vol. 1. 2008. p. 651-656. 4682100 https://doi.org/10.1109/ICCIT.2008.125
Jang, Hyung Beom ; Kashif, Ali ; Park, Myong Soon ; Jung, Sung Woo. / Reliable cache memory design for sensor networks. Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008. Vol. 1 2008. pp. 651-656
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